Epson PX-8 Technical Manual Download Page 255

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Summary of Contents for PX-8

Page 1: ...EPSON TECHNICAL MANUAL PX B H8490021 1 ...

Page 2: ...a variety of applications The system can also be expanded by connecting peripheral equipment such as a printer Long time steady operation has been realized by employing the battery powered supply system with its large capacity of 1100 mAH A recharge control circuit to protect the battery from over charge and an auxiliary battery 90 mAH for backup have been added to enhance reliability MICROCASSETT...

Page 3: ...NTS CHAPTER 1 GENERAL DESCRIPTION CHAPTER 2 PRINCIPLES OF OPERATIONS CHAPTER 3 OPTION PRINCIPLES OF OPERATIONS CHAPTER 4 DISASSEMBLY ASSEMBLY CHAPTER 5 TROUBLE SHOOTING CHAPTER 6 MAINTENANCE CHAPTER 7 APPENDIX REV A ...

Page 4: ...CHAPTER 1 GENERAL DESCRIPTION REV A 1 1 Specifications 1 1 1 2 Name of Major Parts 1 4 1 3 Major Parts 1 5 1 4 Interface 1 8 1 5 Connection Cable option 1 15 ...

Page 5: ...peaker ROM capsule RS 232C SERIAL are not operating Two Ni cd rechargeable batteries Main battery Auxiliary battery Voltage 4 8V 4 8V Capacity 1100 mAH 90mAH Charging current 330 mA MAX 10 mA MAX Charging voltage 5 6 6 4V 5 7 6 0V 6 0V 600 mA 72 keys include 9 function keys 3 mode indication lamps 480 width x 64 height dots 80 x 8 characters per screen 1 64 duty adjustable VIEW ANGLE Tape speed Dr...

Page 6: ...M with battery backup 6kB static RAM with battery backup 32kB Two capsules can be incorporated 8 32kB per capsule 1 1 1 Available models The following models are available for this computer However major differences among these models are restricted to keyboard and AC adaptor specifications the internal hardware is the same Table 1 1 Model Keyboard AC adaptor H101AAA ASCII U S A HOOAAA 120V 60 Hz ...

Page 7: ...l 724 cable For acoustic coupler RS 232C 725 cable For printer RS 232C 726 cable Null modem for interconnection between two EPSON PX 8 computers via RS 232C interfacing CX 20 21 Acoustic coupler PF 10 3 5 inch floppy disk drive TF 15 TF 20 5 25 inch floppy disk drive RAM DISK UNIT Additional 120 60 kB RAM UNIVERSAL UNIT A through hole circuit board and a case MODEM UNIT Built in modem for U S A on...

Page 8: ...neration 12 Analog input interface analog input joystick 3 LCD panel unit 13 Bar code reader interface 4 LCD panel open switch 5 Keyboard unit 14 RS 232C interface for connection to acoustic coupler printer etc 6 Battery cover to replace main battery 7 ROM cartridge cover for replacement of ROM capsule and INITIAL RESET 8 Reset switch 15 High speed serial interface for connec tion to floppy disk d...

Page 9: ...eys Also has three in dicators which show the input mode CD LCD Consists of 480 width x 64 height dots can display a total of 480 characters Main battery A rechargeable Ni cd battery with a capacity of 1100 mAH It supplies power necessary for the normal circuit operation Bottom side Fig 1 2 1 3 1 MAPLEboard Power consumption is considerably reduced by employing power saving C MOS On board inte gra...

Page 10: ... 6Voutput 8 0 0 2W 1 3 2 Microcassette The microcassette consists of a control board and drive mechanism Operations such as FF REW etc are controlled by software resulting in high reliability compared with manual control Increased chip implimentation has permitted a reduction in size of the control board This cassette drive operates at a tape speed of 2 4 cm s and reads or writes data effectively ...

Page 11: ...creen angle can be changed arbitrarily VIEW ANGLE volume is provided to correct the change of liquid crystal dis play condition caused by temperature rise or fall r Fig 1 6 1 3 5 Main battery The main battery is Ni Cd with a nominal voltage of 4 8V When the battery is fully charged the voltage is 5 0V or more enough to provide power for circuit operation The battery can be easily removed and repla...

Page 12: ...22 Keyboard interface CN5 16 LCD interface CN6 8 High speed serial interface CN7 8 RS 232C interface CN8 50 Expansion interface CN9 3 Bar code reader interface CN10 3 Analog input interface CN11 2 External speaker interface Note CN5 is integrated on the back of MAPLE board Table 1 6 CN 1 AC Adaptor Pin Assignments Pin No Signal name Definition 1 VCH Charging voltage 2 Undefined 3 GND Ground Table ...

Page 13: ...supply read amp power supply 3 4 GND Ground 5 RDSP Sound output of read data 6 WE 7 RDMC Read signal 8 WD Write data 9 HMT Head pinch motor control 10 CNTR Counter 11 MT B Capstan motor drive control 12 MTA Capstan motor drive control 13 HSW Head switch status 14 MT C Capstan motor speed control 15 16 VBSW Battery voltage supply for motor 17 ERAH Erase signal 18 19 20 GND Ground 1 9 ...

Page 14: ...can signal 6 KSC 5 Key scan signal 7 KSC 6 Key scan signal 8 KSC 7 Key scan signal 9 KSC 8 Key scan signal 10 KRTN 0 Key return signal 11 KRTN 1 Key return signal 12 KRTN 2 Key return signal 13 KRTN 3 Key return signal 14 KRTN 4 Key return signal 15 KRTN 5 Key return signal 16 KRTN 6 Key return signal 17 KRTN 7 Key return signal 18 LED 0 CAPS LOCK MODE 19 LED 1 NUMERIC MODE 20 LED 2 INSERT MODE 21...

Page 15: ...XECL X enable clock 9 XSCL X shift clock 10 XDO X data 0 11 XD1 X data 1 12 XD2 X data 2 13 XD3 X data 3 14 GND Signal ground 15 16 VL Circuit voltage View from the rear side of the board Table 1 11 CNG High Speed Serial Interface Pin Connections B 76 5 3 4 2 1 Pin No Signal Name Definition 1 GND Signal ground 2 PTX Transmit data output 3 PRX Receiving data input 6 PIN Receiving mode input 7 POUT ...

Page 16: ...2 1 Pin No Signal Name Definition 1 GND Signal ground 2 TXD Transmit data output 3 RXD Receiving data input 4 RST Request to send output 5 CTS Clear to send input 6 DSR Data set ready output 7 DTR Data terminal ready output 8 CD Carrier detect E FG Chassis ground 1 12 ...

Page 17: ...B 1 I O Data bus 1 19 DB 2 I O Data bus 2 20 DB 3 I O Data bus 3 21 DB 4 I O Data bus 4 22 DB 5 I O Data bus 5 23 DB 6 I O Dat bus 6 24 DB 7 I O Data bus 7 25 BURQ 0 Bus request 26 BUAK 0 Bus acknowledge 27 M1 0 Machine cycle 1 28 WAIT I Wait 29 Vl 0 Circuit voltage 5V 30 HlTA 0 Halt acknowledge 31 GND Signal ground 32 GND Signal ground 33 RS 0 Reset 34 SPI I Speaker 35 RD 0 Read 36 MRQ 0 Memory r...

Page 18: ...oltage 3 BRDT Barcode reader data Table 1 15 CN10 Analog Input Interface Pin Assignments Pin No Signal name Definition 1 G Signal ground 2 ANIN Analog input 3 TRIG Analog trigger input Table 1 16 CN11 External Speaker Interface Pin Assignments Pin No Signal name Definition 1 EXSPG Speaker ground 2 EXSP Speaker signal 1 14 ...

Page 19: ... Fig 1 8 Peripheral Device Information Cables Table 1 17 Information Cables Specific to the PX 8 Computer No Interface Part No 723 High speed serial Y204080000 Y204080400 JAPAN 724 RS 232C Y204080 100 Y204080500 JAPAN 725 RS 232C Y204080200 Y204080600 JAPAN 726 High speed serial RS 232C Y204080300 Y204080700 JAPAN 727 Expansion interface Y204301000 1 1 5 ...

Page 20: ...X Brown 6 PIN Orange 4 POUT Blue 7 POUT Blue 5 GND Black 8 6 E CGND Shield E CGND Shield Fig 1 9 723 simple serial cable consists of two lines the send receive data line and the I O control line Therefore devices which can be connected via this cable are intelligent terminals only that is dedicated floppy disk drives that can be controlled by PIN POUT 2 724 cable Usage Connection to acoustic coupl...

Page 21: ...to printer with RS 232C interface Connector Round type miniature DB25 oo 00 0 00 No 1 2 3 4 5 6 7 8 E Signal Name GND TXD RXD RTS CTS DSR DTR CD CG Color Black Brown Red Orange Orange Purple Gray White Shield X 7 Fig 1 11 1 17 No 1 2 3 4 5 6 7 8 20 Signal Name Color CG Shield TXD Brown RXD Red RTS Orange CTS Blue DSR Purple GND Black CD White DTR Gray JI Signal Name Color CG Shield RXD Red TXD Bro...

Page 22: ...R Gray 7 DTR Purple 8 CD White 8 CD Orange E CG Shield E CG Shield Fig 1 12 An shown in Fig 1 11 control lines of DSR and DTR and connected lines of CTS and RTS con nected to CD are crossing respectively Therefore when transmitting data or receiving both un its must open RS 232C interfaces 5 727 cable Usage Connection to optional unit Connector ERC AA50 30 S M d 48 50 am unit SI e I Op o id D M a ...

Page 23: ...REV A ...

Page 24: ...U Operations 2 29 2 4 Clock Generator Circuit 2 50 2 5 Jumper and Switch Setting 2 57 2 6 Reset 2 63 2 7 Keyboard 2 64 2 8 LCD Unit 2 73 2 9 A D Converter 2 85 2 10 ROM Capsule 2 96 2 11 RS 232C Interface 2 100 2 12 Serial Interface 2 108 2 13 Speaker Circuit 2 111 2 14 Dynamic RAM 2 114 ...

Page 25: ...on main and auxiliary battery power supplies Ensures a more reliable battery backup 3 Charge control Prevents excess Ni Cd battery charging 4 Power distribution Outputs the supply voltages only while the computer is in operation in order to minimize bat tery consumption 5 Low voltage detection Automatically changes the main battery to the auxiliary battery supply In addition the computer is provid...

Page 26: ...ED 1320 package RS 232C interface connec 8 CN8 Expansion interface connector tor 10 CN6 Serial interface connector Microcassette interface con 12 V RAM 6kB LCD RAM nector 90 mAH backup battery 14 SW3 Auxiliary battery control switch Main battery connector Reset switch 16 CN1 AC adaptor input charge in put connector GAH40S package 18 F1 Fuse 3A 32 kB x 2 20 Sub CPU 6303 CPU package 8 position DIP s...

Page 27: ...H 40M Microcassette drive Drive mechanism MAP MC board MAPLE board LCD unit IAuxiliary battery I LCD panel MAP LD board IPL ROM I RAM 1 32K 64K I lr 1r V MAIN CPU S2C51 GAH40MJ 1 RS 232C 1 z so 1 n H IiPD 7001 Barcode reader I SED1320 750S 1 I I U J 1 Timer Slave CPU ISED1320 VRAMI I 6303 I 6K I I LCD MASK4K I Microcassette 1 H GAH 40S I I 1 _I tape drive GAH 40S I 1 ROM capsule 1 1 I Speaker I I ...

Page 28: ...s low voltage detection which allows the computer if it is operating to display a warning message CHARGE BATTERY on the LCD screen when the battery power i e vol tage falls below a certain level In addition this function causes the computer to stop at an ap propriate point in the operation in progress The other function determines the normal charge restart timing causing a switch from tricle to no...

Page 29: ...PLE board AC adaptor 7001 7508 Charge control J I F1 f 6 9 Main battery Auxiliary battery GND AID converter To backup circuit RS 232C supply l a power voltage regulator rGAH40S VB 7508 power control ISlave CPU 6303 LCD power Clock voltage generator regulator l L ROM capsule power voltage regulator I GAH40S Fig 2 3 Power Circuit Block Diagram 2 5 r 8V 8V 10 Logic circuit voltage supply 5V Speaker a...

Page 30: ...coincides with that of the clock built in CPU 7508 2 2 1 2 Power Off Power is turned off by one of the following 1 POWER switch OFF Turning the POWER switch OFF causes pin 23 of the 7508 CPU INTO to go low see Fig 2 4 interrupting the control program for turning power off 2 Low voltage detection When a low VB line voltage is detected The 7508 CPU interrupts the main CPU and current processing to b...

Page 31: ... E afji 21 CN 7 n RS232 Fig 2 4 Power On Off Control Circuit The power off operation involves the following component functions Microcasette tape drive head unloading Microcassette tape drive power off P ROM cartridge power off RS 232C power off Barcode reader power off Speaker power off R60 LJ I 71 R12 1 C2Sm K B76543210 71 98765 4 3 21 171 CN K B It also controls the emergency power supply which...

Page 32: ...the POWER switch is set ON or RESET off or an automatic power on or off is input via software the sub CPU control program processes the power on or off as an interrupt using port 70 as follows Power on P70 of the sub CPU 7508 going low causes the anode of 015 to go low turning pin 4 of IC 3E high This in turn causes the output at pin 14 of the next inverter 120 to go low This signal is fed to tran...

Page 33: ... will be resumed without error when power is restored The sequence allows all necessary processes such as the reinitialization of the I O device e g microcassette in operation a warning message display etc to be accom plished before the logic circuit voltage supply is actually removed OFF signal The OFF signal shown in Fig 2 5 is controlled via P71 of sub CPU 7508 This sig nal is emitted to gate a...

Page 34: ...y battery R43 GNO 471 10 9 0 VB Main battery voltage Note c P70 POWER ON signal High turns power off and Low turns power on 8 Fig 2 6 P42 Main auxiliary battery switching signal High selects auxiliary battery and Low select main battery 2 10 To RAM etc POWERSW C64 VOO G POO INTO 7508 2E t P42 5 r T t i P70 REV A ...

Page 35: ...ffectively bypasses resistors R3 and R5 inserted in the charging circuit in series and causes the charging current to be supplied to the battery through transistor 09 current limiting resistor R1 and reverse current preventing diode 04 This setting ecuses the battery to be con tinually charged as long as the AC adaptor is connected Because of the low current limiting resis tance in the mode of ope...

Page 36: ...er switch ON interruption L H r Main battery Low Inactive P23 Out voltage detection High Active Supply main battery voltage to AID converter Supply operational voltage to AID converter Low Reset main CPU slave CPU etc P40 out Reset High Inactive Recharging mode Low Normal recharging mode P41 Out control High Trikle recharging mode P42 Out Battery back up Low Back up with main battery control High ...

Page 37: ...n and power off the circuit remains in the trickle charge mode after the normal charge for the first eight hours However the circuit automatically returns to the normal charge mode whenever the battery vol tage falls below 5V 2 Charging Operations Fig 2 S is a timing diagram which illustrates the main battery charging operation when the charge control is in effect POWER switch setting W 4 0H U AC ...

Page 38: ...ff While the computer is used the battery power decreases depending on how it is used After power off the battery power decreases for backing up the internal circuits CD Situation The AC adaptor is connected while the power remains off The eight hour normal charge starts when the AC adaptor is connected However it is inter rupted four hours after when the adaptor is disconnected The battery is cha...

Page 39: ...er supply Main battery v B Fig 2 9 Auxiliary Battery Charging Circuit ference of approximately 6V VCH voltage which is AC adapter voltage to appear across zener diode Z07 breaking it down Z07 is a 3 3V zener diode This lowers the base voltage of tran sistor 013 below the collector voltage putting the transistor in conduction and providing the normal charging path from the VCH line through 013 012 ...

Page 40: ...f the circuits are described in the fol lowing 1 Protection against low voltage The diode inserted in the charging circuit in series prevents reverse current if the charging vol tage falls below the battery voltage 2 Protection against overvoltage If the voltage at the cathode of the zener diode VCH rises to 7 5V or above the zener diode breaks down and protect the overvoltage condition for VB lin...

Page 41: ...and 032 in conduction 024 feeds the battery voltage VB to pin 16 of IC 1D power terminal pin to enable the AD converter uPD7001 032 feeds VB to the voltage divider resistors R69 and R57 The divided voltage across R57 is fed to the AN 1 channel input of the AD converter which converts the input voltage to a 6 bit digi tal value representing a voltage value from OV to 2 0V in a minimum increment of ...

Page 42: ...69 R57 2 VB x R57 x 250 x 217 4 71 V Note The above expressions do not take into account any errors such as the divider resistance errors etc and they actually include a total error factor of 0 1 V The above low voltage detection is performed regardless of whether power is on or off After the after low voltage is detected port 23 of the sub CPU pin 5 is back low to prevent further battery power co...

Page 43: ...reached a current flows from the auxiliary battery which is connected to the emitter of 03 to the collector i e to the VB line supplementing its power which is being supplied from the main battery This oper ation ensures that the computer operation such as microcassette rewind etc which is in pro gress when low voltage is detected is normally completed The high output from port 42 of the sub CPU i...

Page 44: ... bit AD converter Battery voltage detection and temperature change detec tion for RAM refresh rate determination etc The operating voltage is supplied for a ms every 10 seconds The backup circuit is shown in Fig 2 13 As can be seen the circuit is normally backed up from the VB line via the transis tor Q23 regardless of whether the computer is operating or not It is backed up from the auxi liary ba...

Page 45: ...iled in the following 2 2 5 1 5V Regulator This regulator supplies power to the ROM capsule When accessed the ROM generates such a large transient current that if it were directly powered by the battery a momentary low voltage condition would occur due to a voltage drop along the power line precluding normal operation To prevent this the regulator is provided as a power buffer The circuit operatio...

Page 46: ...r Because this output is connected to the constant voltage circuit consisting of the resistors R13 and R25 and the zener diode ZD5 the actual output voltage is fixed at 5V by the 5V break down voltage of the zener diode When the 04 output voltage rises above 5V ZD5 breaks down at 5V putting transistor 022 in conduction which forces the switching signal to ground level The output voltage is always ...

Page 47: ...or Voltage Waveforms In 5V Regulator Circuit Details of the above waveforms are enlarged below for clarity 5V 5V G U u IJ G f r Voltage circuit 5V 5V GND Fig 2 17 Major Voltage Waveforms Enlarged Though it looks as if 05 continued to oscillate due to false images in the above photograph it ac tually switches once almost every several switching clock pulses This ratio varies depending on load 2 23 ...

Page 48: ...ng a nega tive voltage at the negative side of capacitor C17 This output is used as the LCD drive source voltage It is also fed to the constant voltage circuit which connects the LCD drive voltage to the 5V logic circuit line through the resistor R147 and the zener diode Z020 The zener diode has a breakdown voltage of 20V Thus when the output voltage rises to 15V or LCD regulator output voltage 35...

Page 49: ...__ V8 Return voltage from LCD o 1 4H III regulator J 11 I I Auxiliary battery Q20 _ VB 20K Fig 2 19 Feedback Circuit Fig 2 19 is the feedback circuit redrawn for clarification This circuit provides the charging path to the auxiliary battery while power is on 7508 P70 Power control 7508 P42 Main auxiliary battery switching Feedback voltage waveform as observed Power off Auxiliary battery change 1 1...

Page 50: ...aph of the major voltage waveforms Top Measured at IC 140 pin 7 Center Measured at IC 140 pin 6 Bottom Measured at diode anode REV A 5V 10V 10 5 5V Fig 2 21 Major Voltage Waveforms of LCD Drive Power Regulator Circuit 2 26 ...

Page 51: ...f the transistor Q8 turning it on This causes the battery voltage VB 5V to be output at the collector of the transistor The INHRS signal is inverted high by 12D and then input to the base transistor Q18 cutting the transistor off Q17 is also cut off leaving the transmission line TXD floating A pulse signal of approximately 35 kHz generated by a CR oscillator circuit is supplied to pin 9 of IC 14D ...

Page 52: ...te a constant output voltage When the 8V line voltage is lower no potential difference is generated across the base ground and emitter of the transistor 021 it is maintained in the off state because the zener diode ZD2 does not break down and the switching circuit is not affected When voltage rises to 7V or above however ZD2 breaks down at its zener voltage generating a potential differ ence acros...

Page 53: ...PU 7508 200 kHz The sub CPU provides the following circuit operation control functions independent of the main CPU using the internal 4 kB masked ROM Command exchange with the main CPU via a gate array GAH40M Power on off control Change mode normal or trickle control Keyboard data entry check DIP switch setting read A D converter enabling disabling control 3 Slave CPU 6303 614 kHz The 6303 provide...

Page 54: ...ller Data exchange between l80 and 7508 Handshaking is accomplished via the gate array GAH40M Fig 2 25 Data Command Exchange Between Main CPU and Sub CPUs 2 3 1 1 Data Command Exchange Between Main CPU and Sub CPU 7508 via GAH40M Commands are transferred in parallell between the main CPU and gate array and serially between the gate array and sub CPU 7508 Handshaking among the CPUs is performed via...

Page 55: ...mmand register I O address 01 H and sets FF Operation sequence between the sub CPU and gate array 1 Sub CPU waits until its port 22 goes high this occurs when FF is reset by the main CPU in dicating that main CPU has stored a command in SIO 2 Sub CPU issues the shift clock SCK and reads in the command from SIO one bit at a time and performs the specified processing 3 Sub CPU activates its port 22 ...

Page 56: ...s reset by bit 0 of Z80 I O address 01 SID READY is set by 7508 port 22 The SID READY signal is set and reset either by a command data or interrupt The operations are illustrated by Fig 2 28 Command data START Write command and reset SID FF Termination N N Write or read command Reset SID FF Interrupt START Read status and reset SID FF Read status Check status to determine interrupt type y Fig 2 28...

Page 57: ...ommands of the main CPU and the sub CPU 7508 The operation sequence executed when the main CPU reads data from the A D converter 7001 is shown below 1 Main CPU reads I O address 05 and examines whether bit is on high examines whether a analog data read command may be issued by checking the state of the handshaking FF in the gate array GAH40M bit 0 of I O address 05 If the previous command has been...

Page 58: ...in CPU reads I O address 06 to read in the 1 byte data 2 3 1 2 Data Command Exchange between Main CPU and Sub CPU 6303 via SED1320 Data Commands are transferred in an 8 bit parallel format between Z80 the main CPU and the sub CPU 6303 via two registers in the gate array SED1320 Fig 2 30 illustrates the control flow Z 80 C Read signal OFH Data OEH Write signal CMD OFH Jo Read signal OEH PDOR PDIR j...

Page 59: ...H Read OOOEH OOOFH Wnte 1 S R IBF IBF R S 1 S R OBF OBF cf Q Fig 2 31 Handshaking Between zao and 6303 The status registers are accessed from both l80 and are 6303 and used as follows Output When either the l80 or 6303 outputs 1 byte data the OBF bit of one status register and the IBF bit of the other status register are set This informs the other CPU that the 1 byte data has been stored in the ga...

Page 60: ... Internal RAM 80H FFH I O register 00H 28H Option unit ROM LCD V RAM 6 kB 8000H 97FFH Sub I O control GAH40S Main CPU Z80 IPL ROM OOOOH 7FFFH D RAM OOOOH FFFFH SIO 82C51 I O OCH ODH Baud rate generator GAH40M OOH 07H SED 132D I O OEH OFH I ROM capsule Max 32 kB Fig 2 32 Memory Space 2 36 4 bit CPU 7508 4 kB mask ROM 896 bit memory ROM capsule Max 32 kB ...

Page 61: ...s register 0004 W GAH40M Interrupt Enable register 0005 R GAH40M Status register R GAH40M Serial I O register 0006 W Serial I O register 0007 l Unused 0008 OOOC W 82C51 Command OOOD R W 82C51 Data OOOE R SED 1320 Status R SED 1320 Data OOOF W Command register 0010 l Unused OOFF 2 3 2 1 Reset Three negative going swings of the clock signal supplied at the RS terminal cause the internal ini tializat...

Page 62: ...Option unit Address bus I 1 il 0 liank 0 GAH40D K2 GAH40M 32KB 64KB OPTION Main CPU IPLROM D RAM ROM j I I I I Data bus I L _________ _ Fig 2 33 Memory Configuration The entire memory space is divided into the four banks listed in Table 2 5 which are se lected by a combination of the BANK 0 and BK 2 signals shown in Fig 2 32 Table 2 5 Memory Bank Selection 1 1 0 0 S l to 0 1 0 1 Address FFFF D RAM...

Page 63: ...errupts are controlled in GAH40M from the main CPU by the corre sponding interrupt control bits at I O address 0004 listed in Table 2 6 Table 2 6 Interrupt Control Bits Interrupt Bit name Interrupt Interrupt Bit name Interrupt control bit vector control bit vector 7 Unused 3 IER 3 lCF F6 6 Unused 2 IER 2 RS 232C F4 5 IER 5 Option unit FA 1 IER 1 SID 82C51 F2 4 IER 4 OVF F8 0 IER 0 sub CPU 7508 FO ...

Page 64: ...INT terminal of GAH40D the main CPU makes an indirect call to the interrupt processing routine using the contents of the I register and the read vector address this call is called madkable interrupt mode 2 operation Fig 2 35 shows the signal timing from the time the interrupt is accepted until the interrupt rou tine is entered by the indirect call A concept of the controlling scheme is also presen...

Page 65: ...rupt processing Observed Memory Control Signal Waveforms Top ClK Measured at 4A pin 6 Second from top M 1 Measured at 4A pin 27 Second from bottom MRQ Measured at 4A pin 19 Bottom RF Measured at 4A pin 28 Top ClK Measured at 4A pin 6 Second from top MRQ Measured at 4A pin 19 Second from bottom RF Measured at 4A pin 28 Bottom RD Measured at 4A pin 21 2 41 G G G G 5V 5V 500nS nno no f1JUQl1JU n QJ 1...

Page 66: ...Measured at 6A pin 17 Second from bottom CAS 1 Measured at 6A pin 44 Bottom RF Measured at 6A pin 40 2 42 G G G 5V 5V 2uS JDDDDDf lllJIIOrunru rmon mJITDilllITDITD REV A G 5V 5V Enlarged 5 V 5 V 1 uS G ____ U ___ U ___ Lf ___ G G G J LII__ _ d_ I L 4 1_ __ 5V 5 V Fig 2 38 W1 RAS1 CAS1 and RF ...

Page 67: ...REV A Observed D RAM Refresh Signal Waveforms Top Z RF Measured at 6A pin 29 Bottom FR Measured at 6A pin 40 2 43 5V 2jJS G G_i I_1 I 5V Enlarged 5V tOOnS G G______________ _ l 5V Fig 2 39 Z RF and RF ...

Page 68: ... Control Register Sets the vector address FFFE and the contents of the byte location addressed by FFFF to the program counter Sets the interrupt mask bits A data address is read from the vector address FFFF is sent to the program counter and ini tiates program execution from that address Program Control Register 0003H stores the state of ports 20 21 and 22 used for determin ing the operation mode ...

Page 69: ...l for address 0003 register 6 Speaker Speaker SERIAL SERIAL uMCT uMCT uMCT 0002 I O port 1 port address power POUT PIN HSW uMCTWE ERAH HMT supply output 0003 I O port 2 port address SERIAL SERIAL uMCTWD PRO 3 PTX PRX 0004 I O port 3 data direction I O control for address 0006 register 0 0005 I O port 4 data direction I O control for address 0007 register 0006 I O port 3 port address Address lower ...

Page 70: ... buffer W Controller status register R Port data output register data W Port data input register R Port data output register W command Interrupt enable register W REV A Bit 7 6 5 4 3 2 1 0 Bit15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FLAG IRQ OSS LATCH enable enable Clock control Baudrate control RDRF ORFE TDRE RIE RE TIE TE WU MSB LSB MSB LSB...

Page 71: ... E I E 1f2 I PCS PDIR Parallel Data Input register GAH40M PDOR Parallel Data E AS R W INTR I Output register IR 6303 IW t CSR Control Status CSOE register Fig 2 43 Slave CPU Interrupt Control Block Diagram The INTR signal is generated in SE01320 when the main CPU initiates a command which is in turn fed to GAH40S The signal then interrupts the slave CPU under an interrupt mask control by the slave...

Page 72: ...onverter mode from interface to A D con version This causes the converter to initiate an A D conversion through the specified cnannel The converted result is stored in the shift register in the converter After returning port 21 low the interface mode the 7508 issues shift clock pulses to read in the digital data bit by bit This data is examined to determine the main battery voltage If the voltage ...

Page 73: ...n in fig 2 46 are used to allow the 7508 to perform the following opera tions in order from left to right 1 Fetch the command stored in the gate array GAH40M to 7508 2 Select the tiPD7008 channel 3 Read the A D converted data from tiPD7001 Note Fig 2 46 and 2 47 are enlargements of the signal shown in Fig 2 45 2 49 2V 5V 10mS Fig 2 45 SCK Signal Waveform Serial Data Trans for Enlargement 2V 5V 200...

Page 74: ...equency and Signal Destination Main oscillator circuit CR1 9 8304 MHz 4 9 MHz 7C Clock oscillator circuit CR2 32 768 kHz 1 0 kHz 2E Voltage regulator oscillator 35 kHz 35 kHz RS 232C 8V circuit LCD regulator 1 5V 5V regulator 5V 2 4 1 CR1 Oscillator Circuit The CR1 oscillator circuit starts functioning when power is turned on The output is amplified by IC 7B and is then fed to IC 6A This IC consis...

Page 75: ...the LCD controller 7C and used as the basic clock signal for LCD display control This signal is further halved within the controller The output clock signal of 2 45 MHz is fed to the external clock signal input terminal EXTAL of the 6303 slave CPU Thus the signal is quartered within the slave CPU to a clock signal of 614 kHz and used as its operation clock signal 2V 50mV lOOnS 5V 5V 500nS 6303 f M...

Page 76: ...r power is on or off Fig 2 51 is a circuit diagram of the CR2 oscillator circuit C22 VB R136 R135 CR2 026 IC45 C23 ZD3 C46 4 32 768KHz 025 R36 VB Pull up for RXO signal line on the expansion interface L _ _ _ _ IC 120 pin 14 Power ON OFF control Fig 2 51 CR2 Oscillator Circuit The signal waveforms at various points should be observed as shown in Fig 2 52 The 1 kHz output to the 7508 pin 51 of GAH4...

Page 77: ...transistor Q26 as well as to the base through the resistor R126 A zener diode Z03 is inserted across the base of Q26 and ground Z03 has a zener breakdown voltage of 4V and breaks down when the base potential rises towards the VB 5V voltage beyond 4V The zener breakdown is removed when the base potential falls below 4V An infinite repetition of this alternation causes Q26 to continue switching on a...

Page 78: ... three circuits a RS 232C DC DC converter circuit b LCD DC DC converter circuit c ROM capsule biasing circuit R21 1K 140 140 5 C26 220P 140 2 11 R90 6BK 12 To each circuit a though c discribed above Fig 2 55 Voltage Regulator Oscillator Circuit 5V 10j lS IC 14D Pin 11 D D D G IC 14D Pin 7 D r r r G 5V Fig 2 56 2 4 4 Other Oscillator Circuits Sub CPU 7508 and AID converter have own CR oscillator by...

Page 79: ... 7508 pin 19 G 7508 pin 21 G 5V Fig 2 57 7508 Clock Signal Oscillator Circuit Output Signal Waveforms 2 4 4 2 A O Converter Clock Signal Oscillator This circuit oscillates at a frequency of approximately 480 kHz using an external capacitor and re sistor The signal waveforms at the indicated points should be observd as shown in Fig 2 58 5V 5V 1D pin8 G _______________ I__ _L_ __ _ 1D n 7 I I D QllO...

Page 80: ...Figures 2 59 and 2 60 show the timing relationship among major clock signals 9 8M 4 9M 2 45M 6303 pin 3 EXTAL 6303 pin 40 f E 6303 pin 39 AS 2 45M MRQ M1 RD RF about 100 nsec Fig 2 59 Fig 2 60 2 56 REV A ...

Page 81: ...7 TEST Closed Operates sub CPU 7508 in test mode J4 ON 0 7 Analog Input pull up Closed pulls up ANIN input line to VB through a 100 kohm resistor J5 A B E 6 7 LP pulse hold A Holds 8 LP pulses B Provides no LP pulse holding SW1 OFF C 7 Power switch SW2 N O C 7 Reset switch main frame system rest SW3 ON A 7 Auxiliary battery switch ON Enables backup from auxiliary battery 1 Used to keyboard models ...

Page 82: ...al line reconciling the difference in Line control between the two types of main CPUs The line relates to the DRAM refresh T Terminal T is selected when a TOSHIBA CPU parts No X400084005 is used When the T and center terminals are jumpered the main CPU output signal HLTA is disabled The ter minal is open i e not connected to any other terminal N Terminal N is selected when a NEC CPU parts No X4000...

Page 83: ...ter on and off It is connected to a port of the sub CPU 7508 which controls power on off by sensing a setting change of this switch Thus it may be in effective when the sub CPU loeses the normal power on off sequence control capability because the computer can through a programming error got into a software loop 2 5 2 2 SW2 This is the RESET switch which is accessible at the left side of the compu...

Page 84: ...rwegian 0 1 1 0 0 1 0 0 Italy 1 0 0 1 0 1 0 0 Spain 0 0 0 1 0 1 0 0 HASCI 0 0 0 0 0 1 1 0 Japanese Japanese 1 0 0 0 0 1 0 0 Japanese JIS 0 0 0 0 0 0 0 0 Japanese touch 16 1 0 0 0 0 0 0 0 Note 1 indicates that the switch is closed and 0 indicates that the switch is open SW4 5 is used to check whether the RAM disk contents of the RAM unit are correct ON The check is made when power is turned ON in t...

Page 85: ...supply voltage in order to ensure computer reinitialization in an abnormal condi tion A hardware failure may have occurred if SW5 needs to be pressed 2 5 3 Variable Resistors Three variable resistors are located on the MAPLE board as shown in Fig 2 61 and one each on the LCD unit MAP LD board and the microcassette tape drive MAP MC board totalling five The functions of the individual variable resi...

Page 86: ...ded in order to compensate for change in liquid crystal reaction depending on temperature 2 5 3 3 MAP Me Board Variable Resistor This is the variable resistor located at coordination E2 on the circuit diagram which allows the user to adjust the microcassette tape speed An incorrect adjustment of this variable resistor causes the intervals between tape read and write data pulses to deviate from the...

Page 87: ...gram differs from other computers which are reset directly by a switch operation Fig 2 63 outlines the RESET signal circuits System reset signal VB SW2 SW5 SWr P 6 0 P 0 0 RS INTO o VB INITIAL Z80 related Reset routine ADSNS I Internal Q c co o LO e Q J Q RESETSW Sub CPU IE 7508 2E Clears all registers _ a GAH40D 6A 1 AAA RST I such as timer etc ltr Data Ines oto 7 RSO L Z 80 RS 4A 6303 RS 13D GAH...

Page 88: ...r to prevent inconven iences such as latch of flipflops in the gate arrays etc It provides the gate arrays with the follow ing functions GAH40D Supplies the reset signal to Z80 and 6303 etc Disables the Chip Select signal to the IPL ROM Disables the Z80 read signal line Disables the interrupt signal line to Z80 Resets all FFs Disables all outputs other than the above GAH40M Prevents latching of th...

Page 89: ...U issues a MAKE code When it is pressed for the second time i e it is released the sub CPU issues a BREAK code This is required for the correct keyboard data input because the keyboard input mode is controlled by these keys and the main CPU has to be informed whether anyone of them is in effect Fig 2 65 illustrates a sample sequence of key strokes which includes shift operations in the alphanumeri...

Page 90: ...uto Repeat is enabled This feature is enabled or disabled and the frequency of repetition is selected by software 13 27 42 56 Table 2 13 Upper Code Byte 0 1 2 3 4 5 6 7 8 9 A B Lower Code Byte 0 2 1 29 46 62 21 37 54 12 1 3 14 30 47 63 22 38 55 13 2 4 15 31 48 64 23 39 56 OFF 43 ON 43 3 5 16 32 49 65 24 40 71 OFF 57 ON 57 4 6 17 33 50 66 25 41 58 OFF 70 ON 70 5 7 18 34 51 67 26 42 59 OFF 72 ON 72 ...

Page 91: ...e switch uses a pair of mechanical contacts The spring contact moves left and right to make and break contact according to the vertical stroke of the key stem Fig 2 67 illus trates the rela tionship between make and break of the switch contacts and key stroke The space shift and re torn keys have a press load of approximately 95g while the rest have that of approximately 65g Full break area Make a...

Page 92: ...I 1 C lE 1 1 IJKSeQ 8 0 1 I 1 1 8 D i 1 1 2E I I KRTN 0 7 1 I 1 47K I I AAA _ 5 1 I I 1 1 I J I 1 I 1 VI 47K 5 I I 1 I I 1 1 I A 5 I VI I 47K L_J r MAPLE board Keyboard 0 CN4 Fig 2 68 Keyboard Matrix Normally IC 1E maintains all the KSC signal lines at the low level Pressing a key causes a current to flow from the corresponding KRTN signal line on the MAPLE board to the IC through the diodes pulli...

Page 93: ... decoder IC 1E as shown in Table 2 14 Table 2 14 Input 1E Output A B C D 0 1 2 3 4 5 6 7 8 9 L L L L L H H H H H H H H H H L L L H L H H H H H H H H L H L L H H L H H H H H H H H H L L H H H L H H H H H H L L H L H H H H L H H H H H H L H L H H H H H L H H H H L H H L H H H H H H L H H H H H H L H H H H H H H L H H L L L H H H H H H H H H L H H L L H H H H H H H H H H L 2 69 ...

Page 94: ...according to Table 2 14 5V P30 P3l __ n I P32 P33 I 5V DIP Switch Assembly SW4 Setting Detection REV A 5V 2ms n I n 5V Fig 2 70 This switch assembly forms a matrix of the KSC8 line and the KRTN lines KRTNO through KTRN7 as shown in Fig 2 71 Thus its setting can be read in the same way as a normal key switch Fig 2 71 SW4 Matrix 2 70 ...

Page 95: ...t is accepted until only a single key is pressed Assume for example that the keys A B and C in Fig 2 72 are simultaneously pressed The KSC1 signal will pull both the KRTN1 and KRTN6 lines low it and will not be able to be determined which is pressed The KRTN1 line goes low when the KSC1 line is activated low because the two lines are connected via the A con tacts The KRTN6 line is pulled low durin...

Page 96: ...dicated in Fig 2 73 Their locations and names are printed on the back side of the keyboard board The resistors are located as shown in Fig 2 73 D2 D3 D21 D4 I I I 13 27 28 42 D12 56 D14 69 70 71 72 D16 D23 D19 D22 D20 D18 R1 1 R3 R2 r I Fig 2 73 Note The Auto Repeat feature is ineffective for the following keys See Fig 2 73 2 9 43 57 68 69 70 and 72 2 72 D1 D5 D10 D9 D6 D13 D15 D17 D7 D11 D8 ...

Page 97: ...ress dat RAM r I L__ I Read write I 6 kB control LINE LDO Q 1 0 Oc V drive control 0 Xu Supply voltage 480 dots 64 dots LCD Unit r I 1 Fig 2 74 LCD Unit Control Block Diagram The LCD unit is controlled by the slave CPU 6303 as shown in the above block diagram In the character mode the character generator in SED1320 is used for display In the graphic mode how ever the data from the 6kB RAM are disp...

Page 98: ...o electric field is applied Polarization direction Dark areas where an electric field is applied Liquid crystal molecule Lower glass plate Upper glass plate Lower polarizer plate Fig 2 75 2 8 2 Theory of Operation The liquid crystal is confined between the upper and lower glass plates The upper glass plate has many of electrodes regularly arranged on it The liquid crystal characteristically shows ...

Page 99: ...s in no reflection from the bottom reflector plate so that the panel looks dark black The reaction to the electric field varies depending on temperature To compensate this a variable resistor called VIEW ANGLE is provided in the voltage source circuit Display dot segment Each display dot has an area of 0 45 high x 0 41 wide mm2 These dots are laid out at a vertical pitch of 0 5 mm and at a horizon...

Page 100: ...cal dot matrix and dirven with eight SED1120 X direction vertical drivers and one SED1130 V direction horizontal driver The SED1120 drivers each of which can drive 64 dots are assigned to eight X drive lines X1 through X8 as shown in Fig 2 77 480 dots r 1 33 65 97 129 161 193 225 241 273 305 337 369 401 433 465 J 32 64 96 128 160 192 224 240 272 304 336 368 400 432 464 480 64 Xl X2 X3 X4 X5 X6 X7 ...

Page 101: ...UlfAlULJUUlYtuuuuuV JUUULJUlJ11 16 pulses SED1120 X1 X2 X7 X8 X1 Chip select XSCL DINO 60 ________________ __________ ____ fl _____________ 56 0 DIN1 ________________ ______ ________ rl __________ 57 61 DIN2 62 ____________ __ 7 ______ n ____ 58 2 DIN3 63 7 ________ n ___ 59 3 Fig 2 79 LCD Operation Signal Timing 16 pulses of the data strobing signal XSCL are supplied to each SED1120 driver During...

Page 102: ...s are transferred by a single XSCL pulse 480 dots 4 x 120 x SCL pulses The data bits for one entire dot line in the Y direction are transferred in a duration of 130 f ls A pulse signal LP is generated at the came frequency as the XSCL pulse signal This signal out puts the Y line data output signal YDOO when it is activated This causes the Y line drive position to be advanced by one dot to designat...

Page 103: ... at CN5 pin 7 r _ Second from top XSCL measured at CN5 pin 9 Second from bottom XECL measured at G CN5 pin 8 Bottom XDO measured at CN5 pin 10 G G G 2 79 5V 5V 50 15 0 J I I I nijij ij ijij m Hij nijl 5V 5V 5V QO fl o 5V 5V Fig 2 81 LCD X Line Display Control Signal Waveforms ...

Page 104: ...s display dots are written to the select G ed X drive IC in succession Fig 2 81 shows waveforms of the XECL and XSCL signals on different time base 15 XSCL pulses corre spond to the first XECL pulse and 16 XSCL pulses correspond to each of the subsequent XECL pulses G G G G 2 80 REV A 2V 500mV 50 JS 11111111 11111111 111111111111 11111111111111 2V 500mV 5 lS 111111111111111111111111111111111111111...

Page 105: ...asured at CN5 pin 3 Second from bottom YSDU measured at CN5 pin 4 Bottom YSCL measured at CN5 pin 9 2 81 5V r l 5V 50 JS G G n ij G J G 1111111111111111 11111111111111 5V 5V L _______ J 5V 5V 50J lS G J G _ _ f 1 Jl w J JI lloIoI IoIolI III III 1 1I III___ 5V Fig 2 83 LCD V Line Display Control Signal Waveforms ...

Page 106: ...QA j l l_ 9_ 2QC 9 _ 8 II Fig 2 84 FR Signal Generator Circuit J5 Jumper FR to LCD unit The LP signal is fed to the first stage of the dual 4 bit binary counter IC 9a The signal frequency is divided down to one sixteenth 285 flsec x 16 4 5 msec and is further fed to the second bin ary counter Two outputs are provided from pins 11 20A and 9 2QC of the second counter which respectively have one 32nd...

Page 107: ...Table 2 15 correspond to dot positions on the display screen At least 64 LP pulses are required to display all the dots Thus a data transfer time of approximately 18 2 ms 285 Jis x 64 and the same amount of non data transfer time i e a total of approximately 36 4 ms are required for each 1 panel display cycle The data transfer and non transfer cycles can be altered as shown in Fig 2 86 by changing...

Page 108: ...7 FR Signal Waveforms The proper FR signal should be selected by jumper J5 according to the nature of the liquid crystal display panel If the jumper is improperly wired or not wired at all vertical or horizontal ghost linesmay appear on the screen Select either signal A or B observing which gives less ghost and better display quality 2 84 ...

Page 109: ...he converter is activated Then to accomplish an ac tual A D conversion the following sequence of control operations must be externally provided 1 Channel Selection After activating a low CS signal the first channel selection address bit is supplied via the SI signal line together with one shift clock pulse from the SCK signal line Repeating this opera tion eight times with the adress bit changed e...

Page 110: ... conversion Approximately 12 5 Jis a duration of 5 clock pulses after this the internal CS signal which is used in the sequence controller goes low allowing the converter to be interfaced with the exter nal circuit via signal terminals such as SO and SCK etc The contents of the sequential compari son register have been set to the shift register by this time Thus when the shift clock SCK pulse is s...

Page 111: ...fliUlnJlJljU1JLnmlj I I Min 56 pulses I I I 1 1 I 5 pulses I IE 0 1 J I SI SCK 1 1 ChannelN Address latch I I I SO I IE 1 I I I I The analog signal input to channel N is sequentially A O converted and stored in the shift register in dura tion of time Fig 2 89 l m ...

Page 112: ... Fig 2 90 shows the battery voltage detector circuit The battery voltage VB is fed to Ithe divider circuit which consists of R69 and R57 through the fuse F1 and the transistor 032 The divided voltage is supplied to channel AN1 of the A D converter The voltage drop across F1 and 032 is negligible and the voltage at the AN 1 terminal VAN1 is given as follows VB R57 AN1 R69 R59 AN 1 0 36VB Low voltag...

Page 113: ...nd Rlll RlllVx VRF R 7 6 R l l l Vx VRE R76 Rlll Rlll C K C 5 5 C o L o I ID UPD 7001 2 ERT COJR56JAA Fig 2 91 Temperature Detector Circuit Vx 2 34 8 x 103 100 x 103 100 x 103 2 696 V Potential at point A 010 MA 153 RS8 10K GND The potential A is also applied to the voltage divider circuit consisting of R86 and the thermistor TH 1 which is the temperature sensor The potential at the junction of R8...

Page 114: ...om 00 H to FF H A triggering output TRIG terminal is provided in this interface so that a wide variation of analog devices from a sim ple one such as a joystick to a complicated measurement instrument can be connected The ANIN signal line may be pulled up to the 5V supply via the jumper J4 The input signal is limited from OV to 5V by voltage limiter diodes and high frequency noises on the signal l...

Page 115: ...in detail in the following This interface has a 5V line terminal that can be used to supply the operating power to the con nected barcode reader The supply is controlled by the barcode reader power on off SWBCD signal fed from port 12 of the gate array GAH40M which can be directly controlled by bit B of main CPU address 00 The barcode data signal line is supplied to the AN3 terminal of the A D con...

Page 116: ...main the same Thus the pat tern could be correctly read in principle by supposedly triggering a time measurement mechanism with each pulse measuring the time between the pulses and processing the pulse intervals based on a reference timing obtained from the measurment This sequence of operations are actually accomplished by software as discussed below Barcode Data Processing Read barcode pattern d...

Page 117: ...trigger may be generated at a different point or points on the pulse depending on the BRDT triggering mode selected by the user See Table 2 1 7 When interrupted the main CPU first reads address 0002 to store the lower eight FRC bits in the corresponding lower half of ICA then it reads address 0003 to store the upper Table 2 17 BRDT Triggering Modes Address 0000 BRDT triggering mode Bit 1 Bit 0 pol...

Page 118: ...ware The BRDT signal is also connected to the A D converter converter output is used to examine the barcode data signal for any unacceptable deviation from the nominal voltage levels and has noth ing to do with data read R52 TRIGo r_ P62 10K Analog interface ANIN IJ t GND R106 100K R107 100K J4 9 ONI OFF 5 5 C33rl 10K 5 1 K Barcode interface R23 2 2K Q10 5u C2 2 VB 3 120 Fig 2 96 Barcode Interface...

Page 119: ...REV A Fig 2 97 shows an example of the barcode patterns This pattern is for low resolution of CODE 39 111111111111 IIIJIJIJ IJ II 5 5 55 Fig 2 97 2 95 ...

Page 120: ... 1 I 1 1 t DAO 7 Fig 2 98 l 0 0 CD en en 0 I 6303 oj 130 AB14 AB15 E AS R W V Two 2767 8kB 27128 16kB or 27256 32kB ROM can be mountedto the ROM capsule and are accessed via the 6303 slave CPU as follows The ROMs are addressed using the data address lines DAO through DA7 An address is therefore set in GAH40S in two parts GAH40S has two 8 bit PROM address registers High and Low which can be directl...

Page 121: ... The 5V ROM power supply is controlled via the 6303 by accessing the command register in GAH40S The process is similar to the ROM data read The SWPR signal which turns the power supply on and off corresponds to bit 0 of the command register I O address 0021 H which is under the direct control of the 6303 GAH40S I I Data q ROM 1 I ROM2 V I Slave I CPU t 6303 Address 0021 H 5V regulator SWPR ROM cap...

Page 122: ...are repeated within a short period of time by eliminating the 50 ms wait time required for regulator stabilization Fig 2 101 illustrates an outline of the re gulator control ROM read R g otoe o p l1 0 ms I Hi f l 1 ms ms 3 second 3 second Fig 2 101 ROM Power Voltage Regulator Control 2 10 3 ROM Data Format It should be noted that the logical addresses memory addresses as seen from the main CPU and...

Page 123: ...ull code and has no special meaning This null code is put here merely because the operating system deals with ROM as it would a floppy disk which always contains E5 The null code is written on all floppy disks when initialized 37 in the second header byte position indicates that the file is to be used with this computer Two ROM capsules may be dealt with as a single floppy disk drive By setting th...

Page 124: ... circuit uses the DC DC converter to generate the voltage sources of 8V from the battery voltage 5V for the RS 232C levels Table 2 19 summarizes the relationship between the levels and data signals Table 2 19 Voltage Level Data Signal Timing Signal State Start Stop Bit in Start Stop System 8V 0 On Space Start bit 8V 1 Off Mark Stop bit The interface circuit uses the receiver circuit shown in Fig 2...

Page 125: ...ion interface IiZ BtL 10K t t t I t t _ _ _ _ _ _ _ 3_7_8_4_____ J To gate array 011 SWRS GAH40M MA INHRS 151WA 011 I IOOJ116V 2 CI4 C8 t 16 ERAer 05 3 IDD 02 J6V R 100 h GND VB R c 0 C R T 0 G C X T 5 0 1 x T N G 0 S R 0 R 0 3 8 4 CN 7 RS232 Fig 2 104 RS 232C Interface Circuit 2 101 ...

Page 126: ...ister I O address 00 through a write from the main CPU Table 2 20 Baud rate Generator Settings B t 7 I r Bit 6 Bit 5 rBit4 B B B B Baud 8251 Baud 8251 R R R R TXC Rate x 1 16 Rate x 1 64 RXC G G G G 8251 clock 3 2 1 0 TX RX TX RX 0 0 0 0 1 74545K 1 74545K 110 110 0 0 0 1 2 4K 2 4K 150 150 0 0 1 0 4 8K 4 8K 300 300 0 0 1 1 9 6K 9 6K 600 600 150 150 0 1 0 0 19 2K 19 2K 1200 1200 300 300 0 1 0 1 38 4...

Page 127: ...5 82C51 C Data buffer y f Receive Transmit It T I L Control register y OD I Data bus The transmit and receive buffers can hold only one byte each Thus the main CPU transfers data byte by byte 2 11 2 3 Interfacing The RS 232C and option unit signal lines are connected to the transmit and receive signal lines RXO and TXO and their input and output are controlled by the 82C51 To prevent the two in pu...

Page 128: ...nsmitter DSR RTS CTS Data fl space mark Carrier Receiver CD Fig 2 107 RS 232C Interface Signal Timing Relationship Setting up for Communications The interface set up operations are common to RS 232C transmitting and receiving The SWRS signal from GAH40M first enables the 8V regulator At the same time the INHRS signal is activated to prevent the regulator output from being supplied until it rises b...

Page 129: ...ations line is detected in the receiver modem after passing through a hand pass filter This state is informed to the receiver interface via the Carrier Detect CD signal The interface assumes the Ready to Receiver state and the subsequently arriving data is demodulated by the modem and is read by the receiver interface Fig 2 108 illustrates the sig nal follow including flow over the communications ...

Page 130: ...es low Input signal lines There are the four input signal lines RXD CTS DSR and CD These signals are converted by the limiter diode circuit shown in the figure Mark negative level causes a current through the diode B clamping the input to IC 4049 at the ground level Space positive level causes a current through the diode A to the 5V supply clamping the input at 5V sv RTS 12 3________ _ 0 RTS C31 L...

Page 131: ...witching The transmit receive lines between the option unit if connected are connected to the trans mit receive data lines TXD RXD between the serial controller 82C51 2A as well as to the those lines going to and from the RS 232C in terface as shown in Fig 2 111 These two pairs of lines cannot be controlled simultaneously It is necessary to enable one either pair or no other This is accomplished b...

Page 132: ...by the gate array GAH40M See paragraph 2 5 3 for details of the regulator operation 2 12 2 Data Transmission Rate A baud rate can be determined by varying the internal frequency division of the clock signal to the slave CPU 2 4576 MHz One of four baud rates 38 4K 4800 600 and 150 bps can be select ed The baud rate selection is accomplished by rewriting slave CPU address 0010 the Slave CPU transmis...

Page 133: ... This is required to suppress the regulator output prevent ing its rise time irregular voltage waveform from being recognized as a start bit by the connect ed device The PRX and PIN signal lines have a 1O kohm current limiting resistor a voltage limiter circuit consisting of two diodes and a 100 kohm pull down resistor as shown in Fig 2 113 The current limiting resistor protects the connected devi...

Page 134: ...d PIN signals which respectively indicates whether the computer or the connected device is in the transmit or receive state However these signals will rary depending on the con nected device and or the application program used in the computer See Fig 2 114 Computer Connected device POUT Control signal PIN 1 PTX Transmitted data PRX Control Received data circuit PRX PTX PIN Status Ready signal POUT...

Page 135: ...nternal speaker is automatically switched to the external speaker when the speakel cord jack is connected with CN 11 3 Speaker The built in speaker is a 200 mW 8 ohm cone speaker with a frequency range from 600 Hz to 10 000 Hz Note The BEEP command can specify up to 2500 Hz 2 13 1 Circuit Operations The speaker circuit includes an operational amplifier NJM 386 8B whose operation voltage is control...

Page 136: ...ed to reject the DC component of the incoming signals 2 13 2 System Outputs to Speaker Anyone of the sounds listed in Table 2 23 can be output to the speaker s from the system via the BASIC SOUND command e g n the application program Table 2 23 System Outputs to Speakser Occasion Sound Power on in Restart mode One short sound of selected frequency Power on in Continue mode One long sound of select...

Page 137: ...the volume control variable resistor VR1 at the middle when playing back AZI MUTH tapes 200mV 200mV 200mV 50 S 200mV Fig 2 116 When the variable resistor VR1 is set minimum the RDSP signal has almost the same phase as the output signal at IC3 pin 1 However its phase amplitude decreases as VR1 resistance in creases 2 113 ...

Page 138: ...tor circuit CAS Refresh address counter I Refresh controller 0 RF Fig 2 117 D RAM Control Functional Block Diagram Address lines Each D RAM chip has a capacity of 64k bits permitting only eight lines to be addressed at a time Therefore GAH40D sends the upper and lower eight bits of the 16 bit address lines from the main CPU separately This adress mode is illustrated in Fig 2 118 16 address lines M...

Page 139: ...line 0 7 vJ vJ vJ 7E 60 6E 70 OW 6A Q 1 1 Q RF Bit 6 Bit 4 Bit 2 BitO I OCAS GAH400 W RAS Vl l l Vl l l Vl l l IBank I CAS 50 4F 5E 40 control Bit 7 1 r Bit 5 1 r Bit 3 1 r Bit 1 1 I Data bus 0 7 I Main CPU GAH40M I IPL ROM r Bank 0 L CTLR REG J LJ lJ l Option unit RAM disk BK2 I GAH400 64KB 128KB I I I _ _ _ _ _ _ J ______________ J Sub CPU 7508 I Fig 2 119 O RAM Configuration An external 64kB or...

Page 140: ... sets the states of ports 72 and 73 according to the selected temperature range The range is indicated to the gate array GAH400 which internally generates two re fresh control signals CAS and WE and supplies them to the O RAM chips Table 2 24 sum marizes the relashionship between the modes and the control signals Table 2 24 O RAM Refresh Mode and Contrl Signals Refresh Ambient Control signals to O...

Page 141: ...Menu display Top RF output measured at IC 6A pin 40 Bottom Z RF input measured at IC 6A pin 29 1 1 I 2V I 500nS I I I I G I U I 0 II U I I I I I I G I U U W I I I I I I 5V I L _______ l t 1 Enlarged J 2V 200nS G 1 I G I 5V Fig 2 120 RAS and CAS Signal Waveforms G I G _ _ Fig 2 121 Z RF and RF Signal Waveforms During Menu Display 2 117 ...

Page 142: ...ouput measured at IC 6A pin 40 Bottom Z RF input measured at IC 6A pin 29 REV A 1 1 I 2V I I I G J I L_ I I I I G_ I OL M__ _ I I I 5V I L_______ l 2V GL 5V Fig 2 122 Z RF and RF Signal Waveforms During Read Write 2 118 ...

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Page 146: ...CHAPTER 3 OPTION PRINCIPLES OF OPERATIONS REV A 3 1 MICROCASSETTE 3 1 3 2 RAM DISK UNIT 3 18 ...

Page 147: ...lowing sig nals HSW Indicates the current position of the read write head LOAD UNLOAD WE Indicates whether the microcassette is write enabled detects the presence of the microcassette write inhibit tab ERAH Erase signal HMT Head pinch motor drive signal 0 Write data 3 1 2 Gate Array Functions The gate array issues or accepts the following signals under the control of the slave CPU MTA MTC Capstan ...

Page 148: ...on data for the tape and directory and the second and third blocks contain control data for the files One file consists of a header block one or more data blocks and an end of file EOF block Fig 3 3 illustrates the general data structure of one reel File n t Tape reel volume j Directory I File 0 I File 1 I I File N i First block Second block Third bloCk Tape and directory identification data File ...

Page 149: ...e view J j l Write inhibit tab write inhibited when ___________ _ bent in Left reel L I I I I I I I _ J_J cassette tape Right reel I I I I I Phototransistor _ _ J 0 Reflection plate yJJ Light emission diode HSwswltchx_ J Pinion rack Head pinch 2 HSP sWitch motor t Tape is loaded when the switch breaks Loading unloading is accomplished by slid ing tape on the pinch roller and read write head using ...

Page 150: ...cussed in the following 1 Capstan motor drive circuit This circuit uses two ICs IC1 and IC2 IC1 controls motor drive circuit switching and IC2 controls motor revolution speed Motor drive circuit Fig 3 5 shows the internal circuit of IC1 VB SW MTA MTB QI B r Ie 2 Pin 6 D2 Q4 Q6 M M I I L_J M r 1 J___ 1_ Capstan motor Fig 3 5 Motor Drive IC Circuit The circuit switches the polarity of the voltage ap...

Page 151: ...ver the high level at the col lector of 03 maintains the transistor in conduction this time causing the the M terminal of the capstan motor to be held at ground level The low signal inverted by inverter D turns transistor 06 and supplies the VBSW voltage to the M terminal This results in a backward capstan motor drive which rewinds the tape The motor control transistors 05 and 06 are in conduction...

Page 152: ...1E I I L r J I lSDbO R 3 11 Cl RB o 100 L J 4 IC5 2 64069 This circuit controls revolution of the capstan motor to ensure a cassette tape feed at a constant speed Tape must be read written at a speed of 2 4 cm s To secure this tape speed the capstan motor must revolve at 2 400 rpm Because no tape speed control is desired during fast forward feed or rewind a function which can enable or disable the...

Page 153: ...cannot be con trolled by a pulse signal as the motor would oscillate The IC output is integrated by the next stage integrating circuit which uses the external capacitors C3 and C4 The pulse delay time t is determined by the capacitance of C4 Fig 3 9 Integrating Circuit Current Control The output current from the integrating circuit is amplified and the amplified current is limited to a proper valu...

Page 154: ...chogenerator The relationship bet ween the time constant and the rpm of the capstan motor is as follows NP 1 17RxC7 1 2400 10 1 1 7 Rx 0 01 24 x 103 Rx 1 17 x 0 01 ApproxImately 205 kQ where N rpm of capstan motor 2 400 rpm 3 8 P Number of tachogenerator poles 10 Rx Total resistance of VR1 and R5 kohms C7 0 01 uF pF The specified speed should be attained by ad justing VR 1 nearly at the center The...

Page 155: ... t R8 100 GN0 0 __ CNTR Mirror __ Ie 5 2164069 Fig 3 11 Tape Count Detector Circuit and Positional Relationship between Elements I I 1 I I I I I J The reflector drum has four mirrors on it as shown in Fig 3 11 One reel revolution is counted as four 3 1 6 2 Head Pinch Motor Control The head pinch motor moves the P Iever assembly consisting of the pinch roller and the read write head The assembly sl...

Page 156: ...r continued revolving by inertia the read write head position and the pinch roller s con tacting pressure against the capstan shaft would deviate from the specifications and such failures as read write error would occur The zener diode ZD1 connected at the base of 05 maintains the voltage supplied to the motor below the VBSW voltage approximately 5V A higher motor drive voltage would increase the ...

Page 157: ...Fig 3 14 current State Magnetized polarities on tape Discharge Fig 3 14 Tape Write Current Waveform Writing a value is ultimately generating a magnetic polarity determined by the write current direc tion In order to eliminate interference which may be caused by data patterns previously written magnetized on the tape the erase head is always activated during write operation initiated by the ERAH si...

Page 158: ...f each bit the pull up of the input to pin 5 of IC5 to the VLSW voltage line through R4 The WD signal which represents the logical value 0 or 1 of each data bit usually va ries its level and appears as shown in Fig 3 17 it looks like a train of pulses ON 1 bit 2 kHz cycle OFF 0 bit 1 kHz cycle ON Bit Logical 1 OFF Bit LogcaIO Fig 3 17 Write Signal WD Pulse Train ON Bit The flag bit is also written...

Page 159: ...the capacitor C12 to be charged resulting in the write current through the read write head in the direction indi cated as 12 in Fig 3 16 When the WD signal goes high C12 starts charging and results in the write current indicated as 11 This charge and dischar ge cycle is repeated for each data bit until the complete series of data bits is written The diode D2 connected at pin 12 of IC5 limits the t...

Page 160: ...plifier G The output of this amplifier is fed to the next filter circuit It is also supplied to the speaker circuit on the MAPLE board Since no phase compensation is provided in the previous stages the signal here has some delay In the filter circuit a high frequency component is removed by the T type filter consisting of R26 R27 and C23 and the amplifier circuit The amplifier frequency response i...

Page 161: ...3 pin 1 5 mV DIV Sweep 0 1 Top Measured at IC4 pin 7 200 mV DIV Bottom Measured at IC4 pin 1 500mV DIV Top Measured at IC4 pin 2 50 mV DIV 200 uS DIV 200 uS DIV 200 uS DIV Bottom Measured IC4 pin 1 500 mV DIV 3 15 Fig 3 21 G t 1 t n n n ln LID 0 LTL J Fig 3 22 G _ ____ h A AA A V V V V V G tn D fn n J n I _ JUULJUU Fig 3 23 ...

Page 162: ...C4 pin 5 AC mode 2 V DIV Fig 3 24 The top three are since waves The bottom signal is almost a square wave due to a peak detec tion by a diode inserted across pins 1 and 2 of IC4 Observed noise filter phase compensation circuit signal waveforms AZIMUTH tape Top Measured at IC3 pin Second from top Measured at the center of R26 and R27 Second from bottom Measured at IC4 pin 6 Bottom Measured at IC4 p...

Page 163: ... pin 3 Bottom 400 kHz basic clock signal measured at IC2 pin 2 Top Capstan motor drive voltage input measured at IC pin 2 Bottom Voltage control signal measured at IC2 pin 6 EXPLODED SIGNAL WAVE 3 17 50mV 100mV 1mS A A A G J J J J J V 500mV Fig 3 26 2V 5 ms d G G a sa 500mV Fig 3 27 50mV 100mV 1mS 50mV Fig 3 28 ...

Page 164: ...HZ OH01 40HOOD 40HOoo 40HQH 40H074 E __ E 05 06 1 i 1 MAP RF BOARD UNIT Y20420400000 IBI 1 43VO 8 Fig 3 29 RAM Disk Board Element Lay Out Table 3 2 Major Circuit Element No Element Function No Element Function 1 Connector CN1 Interface the data and address 2 Battery 4 8V 480mAH busses with Main Frame 3 SW 1 Write protect control 4 SW2 Connect disconnect the built in bat ON Protect OFF Unprotect te...

Page 165: ...AO A7 00 07 V TO Main Frame Fig 3 30 RAM Disk Unit Block Diagram The RAM disk unit includes a power supply circuit hand shaking circuits such as an address and command decoders and a status latch etc a DRAM control circuit a interrupt control circuit a data bus input output control circuit two clock oscillator circuits and an I O selector circuit etc Data are transferred between the Main Frame and...

Page 166: ...DB1 Input Data bus line 1 Output Output 19 DB2 Input Data bus line 2 20 DB3 Input Data bus line 3 output Output 21 DB4 Input Data bus line 4 22 DB5 Input Data bus line 5 Output Output 23 DB6 Input Data bus line 6 24 DB7 Input Data bus line 7 Output Output 25 Not used 26 Not used 27 Not used 28 Not used 29 VL Input Logic circuit 5V supply 30 Not used 31 GND Signal ground 32 GND Signal ground 33 RS ...

Page 167: ...es the main CPU Enable disableloRAM write protection ON Enables write protection allows read SW1 ON ONE 4 only OFF Disables write protection allows both read and write Enable disable battery backup ON Enables battery backup allows battery SW2 ON A 6 charge discharge OFF Disables battery backup battery charge discharge is inhibited JUMPERS I _41 __________ 4 ____ I EJo 0 6DK byte setting 12DK byte ...

Page 168: ... With this switch reset OFF the bat tery is prevented from any discharge other than the natural one so that the longest life can be ensured The backup line circuit operates irrespective of the setting of this switch when the switch is reset OFF the line is backed up from the Main Frame battery and its working time may be shortened 2 Battery charging The battery is always charged toward the full vi...

Page 169: ...Frame power AC adapter Battery voltage relation Path Connected VCH 02 Rl 01 OFF Not connected VB1 Vx VB1 03 R2 01 Not connected VB1 Vx Battery CN2 SW2 01 Connected VCH 01 R36 02 ON Not connected VB1 Vx VB1 02 Not connected VBl Vx Battery CN2 SW2 R3 04 02 The backup line is powered either transistor 01 or 02 depending on whether Main Frame power is on or off While Main Frame is off VL is low becaus...

Page 170: ...asynchronously operate either one must examine the status of the other to accomplish a RAM disk read write A function which temporarily stores the data until it is written in RAM disk or read by Main Frame is also required 1 Address decoder The RAM disk is looked upon as an I O de vice by the Main Frame CPU and two I O ad dresses are assigned Fig 3 34 shows the address decoder circuit I o R Q 210 ...

Page 171: ...Read Read data from RAM disk to Main Frame 80 H WR Data Write Write data from Main Frame to RAM disk Unlike the other three the Status Read signal reads the RAM disk status register irrespective of the RAM disk CPU operation directly controlling the register read access and data bus drive The other signals cannot accomplish their functions without intervention by the RAM disk CPU In ad dition any ...

Page 172: ...TE 1 II I RM3 ____ I J_2 3 5 6 7 8 8 80 H DATA 19A M O READ t t tt it98E 8a lwe llhr Hrl A 7 I LlI H I A5 B5 3 BJ 1Y WP Hl 1t 8AI DI 3 JK x8 READ 17 18 19 o 2 2 J 6 7 Fig 3 36 Data Transfer Directions and Control ICs S8 and 98 contain eight tri state D type FFs each The FFs read and latch data from either data bus as arrowed when the CK signal rises When the oc signal goes low the latched data bec...

Page 173: ... O Selector Circuit IC 5C has six outputs whose functions are listed in table 3 8 Table 3 8 I O Selector Logics Read Write I O Port Address Supplied To 01 78 READ 03 98 00 12C 88 01 13C WRITE 02 4C 03 4C 3 27 OUTPUTS INPUTS OUTPUTS SELECT TROGE DATA 2YO 2Yl 2Y2 2Y3 lYl lY2 lY3 2C 8 A 2G H H H X X H X H H H H H H H L L L L L H H H L H H L H L L H L H H H L H H L L L H H L H H H L H H L L H H H L H ...

Page 174: ... circuit and the gate array GAH40D shown in fig 3 38 A15 r AO l 02 W _ i I J 1 I R 1 Momory map 2 I 5 H 68 6 1 I I DO 07 Fig 3 38 Bank Control Circuit I 0 7 l 7 6 1 1 i Ie EOI030EA GAH40D I The bank control signals and the memory map are associated as shown in table 3 9 Table 3 9 Bank Control Signal and Memory Map i 1 1 0 0 BK Address 0 1 0 1 0 1 FFFF FeOO DRAM 2 DRAM 2 DRAM 1 DRAM 1 OFFF IPL ROM ...

Page 175: ...ion Bank selection is accomplished by the program in IPL ROM which accesses I O ADDRESS 02 and 03 which are connected to the Bank Latch to change the latch setting Thus if a bank which allows no IPL ROM access were selected by simply accessing the Bank Latch no subse quent bank selection would be possible In order to solve this problem the bank control pro gram is usually written in the DRAM area ...

Page 176: ...U There are the following interrupt vectors corresponding to the RAM disk command signals Command signal Data Read Command Write Data Write Interrupt vector 02 04 08 Each of these vector address calls a specific routine that processes the corresponding command and data After an interrupt is accepted the D type FF which caused the interrupt 15C or 16C is initialized Fig 3 40 shows the related circu...

Page 177: ... 43 and controlled by gate array GAH40D It is read written and refreshed also while Main Frame power is off in the same way as Main Frame RAM This unit has two DRAM banks of 64 K bytes each and can provide a capacity of 64 K or 128 K bytes Two signals DCAS and DW which determine a refresh mode while power is off are applied from Main Frame IC 9C is provided to ensure the address output that can dr...

Page 178: ...sk unit The Date COM Write sig nal input to terminal 4 indicates whether a data or command received from Main Frame is being processed or not The signal input to terminal 2 from D type FF 12C indicates whether a data is latched buffered to be sent to Main Frame or not ta set da 00 W option tus read sta 81 R Main frame DATA CMD a read dat 80K sta 81 tus read P I GATE 3 1 9 s nU H 4K R 1 Q 112C 5 24...

Page 179: ...16 40 H 9 245 88 1 w N Q I JWr t 8 1 lOA _ll I 9A20 20 rV 1110 40H 244 20 I 40 4 11 I o DC I 0 4 I 5 0 C I 06C I O H36 I C 40 7 8 4069 4OH074 8 40HI 7 4OHOO2 40H027 9 9 20 UI IP 4 4 O 06 I I I 2 I 04 M IIA 12A I3 A 40HOOO 40H074 10 1 MAP RF BOARD EOI030 181 H3VO I I E I 02 SW2 I C2 r Cl J 15A 16A I I C 40HOOO 4011074 40H074 UNIT 01 04 E 8 E I 07 i4 De i D9 i Y20420400000 REV A 3 33 ...

Page 180: ...151 1 AS t bJ HiSS 5Cl a 123 0123 V O 9ftl l c i 7 t Q 5 r I ttttt r _31 c I Cl U H I I 1 J I I 1 Jill 1 r AOll 5 A6 1 9101IJ ncn A I 0 f JTI TI _ d1 i gl r 71 st sr1 1 R35 rr 31 K l l I H o o 7 I 78 f G2 1 13417 WRI r P OTE w E 11 I I J I Il 10 9 7 7 7 o C EOIOJOlA G H40D tftttW 11 G H MAP RF BOARD Y204204001 A ...

Page 181: ...CHAPTER 4 DISASSEMBLY ASSEMBLY AND ADJUSTMENT REV A 4 1 Main Frame 4 2 4 2 Disassemble Assemble of Each Unit 4 8 4 3 Option Unit 4 1 6 4 4 Main Battery 4 18 ...

Page 182: ...d care must be used to prevent any shortcircuit on the board 5 Avoid placing boards that incorporate ICs MAPLE board LCD panel board option board etc directly on a work stand If it is not practical place it with the component side below so that static electricity will not affect it 6 Pay attention so that cables may not be caught by case fitting poles etc 7 When fitting a screw pay attention to th...

Page 183: ... Remove seven screws pointed by arrows Step 5 Lift up the lower cover from the right side SW panel button I REV A Assemble Procedure Step 1 Same as step 1 of the disassemble procedure Step 2 Remove switch panel and button of power switch Step 3 Fit handle to lower case Step 4 Fit lower case from speaker volume knob side left side Step 5 Fit seven screws pointed by arrows Step 6 Fit switch panel an...

Page 184: ...ed by ar rows Step 6 Lift up board slowly from your side Fig 4 3 Fig 4 4 4 3 Assemble Procedure Perform the reverse procedure to disassem ble Fig 4 2 Step 1 Place PX 8 with lower case being removed Step 2 Put jack connector CD into specified hole Step 3 Place board slowly Step 4 Fit three screws pointed by arrows Step 5 Fit cables to connectors CD CD and CD Step 6 Remove lock button cover and inse...

Page 185: ...ve lower case board and mi Step 1 crocassette Remove four spacers pointed by ar rows and two cassette fitting poles Step 2 Lift up shield board slowly r Fig 4 6 4 4 REV A Assemble Procedure Place the machine so that the batte ry is situated in the right rear corner First align the position of right bot tom screw next top screw and last left bottom screw Place unit slow Iy Fit three screws pointed ...

Page 186: ...m microcassette side I Fig 4 7 Step 1 Remove lock button cover and con nector CN4 Step 2 Lock LCD unit Step 3 Remove screws in the order Q CV and Step 4 Release LCD unit lock and lift up unit slowly from lock side with LCD face up Fig 4 8 4 5 Step 1 Fit travel ratchet as shown in Fig 4 9 Ratchet spring seat 1 Ratchet Ratchet guide pin spring Fig 4 9 Travel ratchet Step 2 Fix LCD unit ratchet to th...

Page 187: ...ctor and next main frame side connector Step 3 Remove four screws pointed by arrows Fig 4 13 4 6 REV A Assemble Procedure Step 1 Remove connector covers both of option and main frame Step 2 Fit option unit as shown in Fig 4 14 and tighten screws tentatively in the order of CD to ill on Fig 4 13 and last tighten them fully Step 3 Fit connector first to option side and second to main frame side Stpe...

Page 188: ... Keyboard cover r Sh __ Cable set Battery cover Handle ROM cartridge cover Overview Fig 4 15 4 7 LCD unit k button cover Loc E Lock lever Microcassette Keyboard Speaker Maple board k volume knob Spea er tor cover Bus connec Lower case Stand tch button Powerswi Switch panel ...

Page 189: ...screw driver between key tops and lift up one end of corre sponding key Lock can be removed Step 3 Shift key and remove it from support bar 3 SPACE key Step 1 Remove key tops Z X C V B N which are located on the top of SPACE bar Step 2 Insert a thin minus screw driver between key tops and lift up one end of key Lock can be removed Step 3 Remove key from support bar using a little screw driver 4 SH...

Page 190: ... Step 1 Step 2 Step 3 Remove microcassette mounting bracket by loosing three screws which are marked with arrows on Fig 4 19 Mounting bracket Fig 4 19 Remove C support bracket by loosing two screws Remove M belt Lift up C wheel slowly C support bracket Fig 4 20 4 9 C wheel ...

Page 191: ...CD and CD Lossen screws 1 and CD Pay attention to two FG spacers FG york C support bracket 3 PE switch Step 1 4 HP switch Step 1 Step 2 Fig 4 21 Remove one screw and PE switch ti I I Fig 4 22 Remove screw pointed by arrow Remove HP switch slowly Screw II o Fig 4 23 4 10 REV A FG york M pulley ...

Page 192: ...6 Pinch roller Remove HP motor Step 1 Step 2 Remove E ring and lift up PR lever and spring PR lever Sp ng f Ering Fig 4 25 7 P lever head part Step 1 Remove HP motor and pinch roller Step 2 Push E button spring by tweezers and remove lever from CD in a way like pulling out CD Fig 4 26 4 11 ...

Page 193: ...r 8 Pocket Step 1 Step 2 Remove pocket spring Remove pocket pin REV A Fig 4 27 4 12 ...

Page 194: ...P switch Screw r Cam gear assembly P support spring Pleversupport A 4i l E PR lever spring 3i o f I E ring P lever Screw Pin o r e Main frame o I I I I 1b t I Switch l I W a s h e r Washer M pulley i Screw ii FG spacer FG york lJ IooE M belt Screw C wheel c support bracket Screw Fig 4 28 4 13 ...

Page 195: ...5 Remove four screws pointed by arrows and lift up board slowly Pay attention to contrast button and cover glass Fig 4 30 Step 6 Move leg of fitting bracket Fitting bracket Leg of fitting bracket r LCD panel MAP LD Zebra board Step 7 Step 8 Step 9 Fig 4 31 Remove fitting bracket with LCD face up Remove LCD with zebra on it taking care for three pins Remove four zebras and zebra guide 4 14 REV A ...

Page 196: ...REV A Overview of LCD Unit Screw Screw Fig 4 32 4 15 Cover panel ____ Upper case 1 Cover glass J Fitting bracket t i Panel 1 Zebra VI E f Zebra X ...

Page 197: ... 3 Step 4 Step 5 Remove unit from the body Remove three screws pointed by arrows Fig 4 33 Remove case cover from screw side Remove two screws pointed by arrows Fig 4 34 Lift up unit slowly from the opposite side of connector 4 16 REV A ...

Page 198: ...REV A Overview of Option Unit 5 Cable set 727 Expansion case 1 Fig 4 35 4 17 Expansion case cover 1 I I I d I ...

Page 199: ...r and remove Step 3 Step 4 Step 5 I the cover Fig 4 36 Main BatteTY Cover Removal Make sure that the auxiliary switch is set Fig 4 37 Auxiliary Battery Switch Disconnect the battery connector and remove the battery o I II J Fig 4 38 Main Battery Removal Connect the new battery connector and put the battery in place and lay the lead wire as shown in Fig 4 39 lay the lead wire so that it is pushed a...

Page 200: ...the ROM capsule cover o CJ o 0 ROM capsule cover Fig 4 40 ROM Capsule Cover Step 9 Push once the INITIAL RESET switch located above the ROM cover Fig 4 41 Access to INITIAL RESET Switch Step 10 Replace the ROM capsule cover After above procedures change the battery by connecting the AC adaptor Never discard the bat tery into water or in fire nor disassemble 4 19 ...

Page 201: ...r CHAPTER 5 TROUBLESHOOTING REV A 5 1 An Introduction to Troubleshooting 5 1 5 2 Test Program 5 1 5 3 Check out Procedure 5 1 5 5 4 Unit Troubleshooting 5 19 ...

Page 202: ...tacts Second isolate and replace the faulty component in the unit according to the appro priate unit flowchart or the trouble table Step 1 Check out procedure Repair by unit replacement Step 2 Unit repair flowchart Repair at com ponent level Note 1 All checks indicated on the flowchart must be made Should any unit or component be replaced disregarding any check the newly installed one might be dam...

Page 203: ...NPUT CHECK 9 BARCODE CHECK 10 CLOCK CHECK 5 2 1 Repairing Tools Table 5 2 lists necessary repair tools which are available from EPSON Table 5 2 Repaired Repair Tools Tool Q ty 1 Test program ROM 1 2 RS 232C interface mini wrapping connector 1 3 Serial interface mini wrapping connector 1 4 Microcassette tape 1 5 Cable assembly PIN B778400201 1 6 DC regulator or dry cell battery 1 7 Low resolution b...

Page 204: ...sJI oJII IIIG IIH II IIIK C I _ 111 111 III IIlvJI III IIIM III III 11 111 11 J Ii JII III II Fig 5 1 Set up for Repair 5 2 2 Installing the Test Program ROM To install the test program ROM in the ROM capsule of the computer perform the following steps Step 1 Reset the POWER switch OFF Step 2 Remove the ROM capsule cover from the bottom panel Step 3 When two ROMs are already installed in the capsu...

Page 205: ...and check to see that the menu shown in Fig 5 5 appears on the LCD panel The display varies depending on the inserted ROM If nothing appears on the panel press the RESET switch C r 1L J j 1 I H i Fig 5 5 Tet Program Menu ivi _ l Move the cursor so that MAPTST blinks and then press the RETURN key CU 1 CD Note One of the messages shown in Fig 5 6 will be displayed depending on the ROM capsule socket...

Page 206: ...rding to the number of times specified in response to the prompt MANUAL Mode Fig 5 8 Prompt for Number of Test Cycles TEST PROGRAM SELECT F b ER LHECX 5 r IL IT CH CI 7 KEY BOARD CHECK 9 II Bi lnCDDF HF C I BUZZ F CI IJ CV 4 LCD n ILe 6 DIP SW READ CHECK B ANALOG INPUT CHECK 1 j C L C i 1 C I Fig 5 9 Menu for an Individual Test Select a test by keying in the number preceding the test When the test...

Page 207: ...d Serial Interface Check Step 1 Insert the RS 232C serial interface connector which is connected according to the instructions in section 5 1 The RS 232C socket is labeled on the PX 8 case Step 2 Key in 3 for the test menu TEST PROGRAM SELECT The RS 232C and Serial Interface Check test will be selected The program runs the RS 232C interfa ce test first displaying the following information F 2 2L C...

Page 208: ...tern 5 MCMT Microcassette Tape Drive Check The following prompt appears 10 l j Fig 5 16 First MCMT Check Test Prompt If speaker sound output is desired depress Y YES if not press N NO respond by in putting Y YES on N NO as desired The next prompt will appear as follows IS THIS TEPE INITIALIZE Fig 5 17 Second MCMT Check Test Prompt Examine the tape and respond with Y to this prompt if the tape data...

Page 209: ...tch setting agrees with the following table Table 5 3 DIP Switch of Settings SW4 Character set specification 1 2 3 4 5 6 7 ASCII USA 1 1 1 1 0 1 0 French 0 1 1 1 0 1 0 German 1 0 1 1 0 1 0 English 0 0 1 1 0 1 0 Danish 1 1 0 1 0 1 0 Swedish 0 1 0 1 0 1 0 Norwegian 0 1 1 0 0 1 0 Italian 1 0 0 1 0 1 0 Spanish 0 0 0 1 0 1 0 HASCI 0 0 0 0 0 1 1 Japanese Japanese language 1 0 0 0 0 1 0 Japanese kana 0 0...

Page 210: ...70 71 72 Fig 5 23 Keyboard Check Test Character Data Entry The numbers within the parentheses are for a 73 key keyboard When the key data entry ends the following prompt appears h i r 1 J Fig 5 24 Keyboard Check Part 2 Test Entry Prompt Step 3 If the keyboard check part 2 test is desired respond with uN to this prompt Other wise key in Y The above part 1 test will be repeated The program enters th...

Page 211: ...he reading If a dry cell battery is used measure and compare its voltage 9 Barcode Check The following is displayed Fig 5 27 Barcode Check Test Prompt Step 1 Read the barcode pattern using a reader If the pattern and read data agree OK appears on the LCD panel 10 Clock Check The following prompt appears Fig 5 28 Time Setting Prompt Step 1 If you would like to seft the time respond with Y to this p...

Page 212: ...the de fined system 03 Communication error Indicates that a command is received when data was to be recei ved sent or vice versa 11 Illegal size Indicates that a screen over occured which is attributable to an illegal size specification 12 An undefined graphic alphabetic character was used 13 An alphabetic character code was used Or an attempt was made to define any other than that for alphabetic ...

Page 213: ...ck data did not agree 3 RS 232C and Serial Interface error messages I RS232C CHECK TIME OUT Fig 5 34 RS 232C transmission reception failure DIR DSR RTS __ CTS CD TXD RXD I RS232C ERROR TRNSMIT RECIVE N RS 232C transmitted received data failed to agree An RS 232C error code XX 108 10 20 Parity error Overrun error Framing error 1 1 I Cii j F E E D E r I 1 L J C E F r J F T r j j I i I T D j T f H K ...

Page 214: ...ERROR I Fig 5 40 Read write head loading unloading failure Fig 5 41 Tape feed failure during read write the reel stops rotating MCMT READ WRITE CHECK ERROR RDC ERROR CODE Fig 5 42 Read write error possibly an abnormal tape feed speed or improper read write pulse width rO j j 1 r ro r c J 1 J c n r r BLOCK COUNT TO Fig 5 43 Compare error written and read back data failed to agree THIS TAPE CAN T WR...

Page 215: ...hart instructions lead you into a loop or to the end of a procedure and the problem is not resolved refer to the schematic drawings or proceed by troubles shoo ting according to the following procedure Step 1 Replace the faulty unit with a good one and make sure that the faulty unit is really mal functioning Step 2 If the problem is difficult to reproduce or occurs so briefly that it is hard to ex...

Page 216: ...t Press INITIAL RESET switch Turn POWER switch ON Press RESET switch Y GOTO 2 1 N N Adjust VIEW ANGLE variable register Y Press RESET switch 5 15 N Table 5 1 SYSTEM INITIALIZE ENTER DATE TIME YYMMDDhhmmss QOOOOOOOOOOO GOTO 3 1 GOTO 4 2 ...

Page 217: ... menu appear y y y y y GOTO 3 1 5 16 Observe fault pheno menon again before determining that com puter really has a trou ble Then isolate faul ty unit by replacing LCD unit MAPLE bo ard and Microcasset te tape drive in this or der REV A y y y y y ...

Page 218: ...LE var iable resistor as view ing LCD panel Turn POWER switch OFF Then remove main battery and mea sure its output volt age Connect ac adaptor and then press INITI AL RESET switch Charge main battery for 8 0 hours with POWER switch OFF N 5 17 N Feel main battery sur face for any abnormal heat with your fingers y N ...

Page 219: ...switch SW3 ON Readjust VRF voltage with VR2 Set switch SW3 ON press INITIAL RESET switch and then turn POWER switch ON y Replace MARPLE board Replace keyboard unit 5 18 Replace test program ROM press RESET switch and then re load test pregram N REV A ...

Page 220: ...ontinuity or element function with a circuit tester make sure that the line or element to be tested is not backed up by battery Whenever the battery backed up line has to be checked remove the auxiliary battery from the board before the test Others Depending on location of the problem a MAPLE board failure may present various symptoms and troubleshooting is harder Check the computer for any basic ...

Page 221: ...If a definite phenome non can be observed go to the correspond ing entry Otherwise check the following in sequence 5 20 The trouble is possi bly in another unit or connection Replace MAPLE board to recheck whether the trouble is MAPLE board or not REV A ...

Page 222: ...o a defective ele ment Find and re place defective ele ment through visual check and physical feel for excessive heat 5 21 Connect ac adaptor and start 8 hour charge If main battery is bad open jumper J72 overcharge control y Measure main battery voltage with ac adap tor connected loaded voltage and discon nected unloaded vol tage Possibly an open cir cuit in charging cir cuit Replace ac adaptor C...

Page 223: ...her than VB is output Check levels of pins 2 and 15 of IC 12D Replace IC 4C GAH40M Check level of IC 13E pin 31 Check transistors 011 027 and 01 y Check transistors 07 08 014 017 018 021 and031 andre place defective one Replace IC 13E Replace slave CPU 6303 13D y Check signals of IC 14D pins 14 and 15 Replace IC 14D 5 22 REV A Replace IC 12D y Check transistors 04 05 019 022 and 028 and replace de...

Page 224: ...REV A Check signal of IC 14D pin 2 Replace IC 14D Check signals of IC 14D pins 6 and 7 Replace transistor 034 Replace zener diode ZD20 5 23 Replace transistor 029 Replace inductance L3 y GOTO Start ...

Page 225: ... Replace IC 6A Replace main CPU 4A Check pin 6 signal of IC3D N GO TO Start Replace IC 7C Replace IC 2C Replace CR2 Replace IC 5D y 5 24 REV A Replace IC 7B Replace IC 6A Replace IC 6A Replace IC 4C Replace IC 3E Replace IC 6A ...

Page 226: ...REV A y Possibly no clock sig nal related trouble Replace sub CPU 7508 2E Replace A D converter 7001 1 D 5 25 Replace IC 6A N GOTO Start Replace sub CPU 7508 Replace IC 4C ...

Page 227: ...h SW4 is cor rectly set Replace IC 1E y Replace sub CPU 7508 N Reset SW4 y Type all keys Replace IC 1E 5 26 Check outputs of pins 10 through 13 with one malfunctioning key held down Check outputs of IC 1E pins 1 through 11 with above key held down REV A N N ...

Page 228: ...REV A Check pins 8 and 14 potentials of IC 120 y Replace IC 2C Replace transistor Q14 Replace IC 4C y y Replace IC 12C Check signals of IC 120 pins 15 and 16 5 27 ...

Page 229: ... pins 8 and 14 Replace IC 12D Replace IC 9B Check voltage VRF Measure pin 16 vol tage of AD converter 1D Replace A D converter 1D 5 28 9 4 Replace slave CPU 6303 Replace SED 1320 7C Replace V RAM chips 9C through 11 Cone by one REV A y y GOTO Start ...

Page 230: ...ace SED1320 7C GOTO Start Test speaker output by operating micro cassette tape drive and using SOUND command 10 4 Replace sub CPU 7508 2E Replace gate array GAH40D 5 29 y N 10 2 Replace one of the follo wing ICs according to the error bit Bit 0 7D Bit 2 6E Bit 4 6D Bit 6 7E Bit 1 4D Bit 3 5E Bit 5 4E Bit 7 5D ...

Page 231: ...11 1 Replace slave CPU 6303 13D Measure pins 1 and 15 voltage of connec tor CN3 Check transistors 027 011 andOl and replace any defective ones Replace IC 13E 5 30 REV A ...

Page 232: ...e solder from the IC terminal leads with a Solderwick 2 Lightly push the IC up with a precision screw driver Do not force the IC otherwise the printed board and the repair may become impossible circuit pattern may come off the 3 Remove the IC and remove the reamining solder from the pattern with the solder wick 4 Bend the new IC terminal leads so that they fit to the pattern holes The terminal lea...

Page 233: ... problem is found take proper action If no problem is found run test program to find any malfunction End 64 REV A 480 dots 33 65 97 129 161 193 22 S S S S S 32 64 96 128 160 192 224 24 336368 xi x2 x3 x4 x5 x6 x7 x8 xi x2 x3 x4 x5 x6 x7x8 SED 1130 5 32 64 dots ...

Page 234: ...on nectors for any imper fect contacts and then replace LCD unit Possibly a MAPLE bc ard problem 5 33 Measure relative vol tages from 5V of pins 66 67 68 71 and 72 of SEDl130 Yl Measure resistances of resistors Rl through R3 Possibly a short cir cuit within LCD driver Xl toX8 orYl Y Measure maximum voltage between pins 66 and 74 of SED1320 as sliding view angle variable re sistorVR1 Check variable...

Page 235: ...es between cable end and SED1130 pins 3 2 Disassemble LCD panel Examine as sembly of board Ze bra and panel for any problem and check for dirt Clean dirt and or readjust as sembly if necessary Replace SED1120s X1 to X8 for missing columns 5 34 Check the output signal line of SET 1120 which has relation with illegal display function y Replace SED1120s to left of that for missing column REV A ...

Page 236: ... circuit on a KSC or KRTN line or lines Refer to 5 4 3 Re pairing The Key board Reset SW4 and then press INITIAL RESET switch GO TO Start GOTO 2 3 Check to see whether trouble is caused by row or column drop in LCD y Check whether char acter always changes at the same position Replace LCD panel Replace SED11 20 X1 to X8 for column s of trouble GOTO 2 5 5 35 y Check continuity of FPC cable Replace ...

Page 237: ...Reset jumper J5 set ting on MAPLE board Replace LCD panel Replace SED1130s for rows of failures GOTO 2 5 5 36 REV A N 5 2 N ...

Page 238: ...tern separation If damaged components which cannot be repaired are found in steps 1 or 2 replace the keyboard If any foreign matter was found in check 3 clean and dry the components at the normal temperature After components are dry test the keyboard functions again If a problem still exists replace the keyboard Even if the trouble disappears it is possible that it may reoccur at another time due ...

Page 239: ...e quired Test keyboard with test program to evalvate all functions I Byte 1 Lower Code 0 2 Byte 0 7 1 29 1 3 14 30 2 4 15 11 3 5 16 32 4 6 17 33 5 7 18 34 6 8 19 35 7 9 20 36 8 9 5 38 3 46 47 48 49 50 51 52 53 REV A 27 56 4 5 6 7 8 9 A 8 62 21 37 54 12 63 22 8 55 13 64 23 39 56 OFF 4 1 ION 41 65 24 40 71 I OFF 57 ION 57 66 25 41 58 IOFF 70 ION 70 67 26 42 IOFF 72 ION72 10 27 44 60 IOFF HR ION6R 11...

Page 240: ... pearance and stroke of all individual keys Replace that key Check all keybaord functions with test program Replace keyboard unit y Resolder that key switch 5 39 N Remove keytop of that key and check in side for any foreign matter ...

Page 241: ...nnector pin 21 or 22 and KRTN lines 0 through 7 N N 3 2 Possibly a short cir cuit in FPC cable or printed pattern on cir cuit board Check in sulation between all LED anodes and KSC lines Substitute a known good key board and retest GOTO 2 5 5 40 y Inspect soldering of that line and remove short circuit Possibly a trouble on MAPLE board Follow check out procedures again to isolate faulty unit REV A...

Page 242: ... that line Measure line resistance with diodes in forward direction N N N All keys cannot be typed in Examine continuity of FPC cable signal lines including connector contacts N N Replace bad diode 5 41 Check KSC and KRTN lines for that key for any short circuit with another signal y ...

Page 243: ...ey once Press CAPS LOCK key once N N N Press CAPS LOCK key once Make sure that resis tance between key board connector pin 21 GND and each LED cathode is ap proximately 1 kohms Also check that re spective resistances between pins 18 19 and 20 and anodes of three LEDs are 0 ohm 1 3 5 42 REV A ...

Page 244: ...to make sure malfunction is not due to a damaged tape 3 Make sure that the lead wires from the mechanical section are perfectly soldered 4 Examine the error message on the LCD panel to find whether the trouble is a directory related problem Tapes written by other computers may contain no directory and cannot be read by this computer Problems 1 and 2 above are interrelated so that both the checks s...

Page 245: ...MICRO CASSETTE UNIT REPAIR ENTRY TABLE 5 44 Cassette tape drive unit has no trouble Test read write using a work tape REV A ...

Page 246: ...t forward and rewind operations while visually check ing reel operation Does not reel at all Check input voltage at pin 14 of IC2 Check output level at pin 6 of IC2 Is that level low or are pulses approximately 0 1 V observed N 5 45 Perform play opera tion SAVE or LOAD while observing reel motion Check output voltages at IC1 pins 3 through 8 Measure capstan re sistance y N y y Replace capstan mo t...

Page 247: ...e mechanism Check reel for proper rotation during PLAY and rewind or fast for ward operation Possibly no reel rota tion failure Y Unload read write head by breaking or power off Y Possibly no head load unload failure N 5 46 Y Measure base voltage of transistor Q2 Disassemble and check P Iever assem bly for foreign matter in sliding area PLAY drive while ob serving REV A ...

Page 248: ...k zener diode ZD1 Check IC5 pins 5 and 6 y Replace transistor 03 Measure resistance of HP motor winding Replace HP motor l y 5 47 GOTO 3 5 Replace IC5 Replace capstan mo tor Readjust engagement between C shaft and reel gear Possibly a reel failure Replace microcassette tape drive mechanism ...

Page 249: ...nce of read write head wind ing Replace IC4 Replace capacitors C11 through C13 in order 5 48 Readjust azimuth y Adjust tape feed speed Possibly tape is bad or MAPLE board has a problem Clean read write head and pinch roller Then test read write again REV A Replace P Iever as sembly ...

Page 250: ...gnals of IC5 pins 12 and 13 Are pulses observed at those pins which are opposite in phase Replace diode 06 N N Check continuity of diode 02 5 49 Replace transistor Q4 Is LEO always on Replace LED y y Replace C shaft ...

Page 251: ...nother test If micro cassette tape drive mechanism Read write head is not unloaded Press INITIAL RESET switch Replace reflector plate microcassette tape drive mechanism Replace IC5 Replace microcassette tape drive unit cover plate Possibly an EJECT mecanism problem 5 50 Y Replace photo reflector FT1 Replace diode D7 REV A Replace 06 ...

Page 252: ...tangular How to adjust the PE switch 1 Mounting position Fixed spring plate 0 15 0 1 Unit mm L Sep atm The separator must rest on the base plate Cam IAfter mounted I The fixed spring plate must rest on the cam face The separator must rest on the protrusion face When the separator is inclined rest it flat on the base plate If the contact plate is bent stretch it straight 5 51 ...

Page 253: ...of 0 2 or more between the G lever and the switch contact plate approximately twice the switch contact plate thickness which is 0 1 2 lever b When a rug bent cassette tape is inserted 0 3 0 5 Unit mm The separation between the separator and base plate must be from 0 3 to 0 5 approximately half or one third of the separator thickness 5 52 REV A ...

Page 254: ...REV A ...

Page 255: ...6 MAINTENANCE REV A 6 1 Repair 6 1 6 2 Repair Tool and Equipment 6 2 6 3 Soldering 6 3 6 4 Component Locking 6 7 6 5 Notes on Repairing Replacing the MAPLE Board 6 8 6 6 Microcassette Tape Drive Adjustment 6 11 ...

Page 256: ...er removing the circuit board from the case for repair rest it on insulative material to pre vent shortcircuits After turning off the power switch the RAM and a part of IC are backed up by the battery Therefore it is necessary to observe the precautions listed above while replacing elements on the control board Before examining the circuit check to see if the signal lines are backed up Flexible pr...

Page 257: ...d Tweezers MM 125 mm 1 Repair of microcassette Yes Phillips head screwdriver set 1 Repair of microcassette Yes Flat blade screwdriver set 1 Repair of microcassette Yes Pincette MM 125 mm 1 Repair of microcassette Yes Phillips head screwdriver No 100mm 1 Disassembly and assembly Yes 2 of case 81ade screwdriver No 2 100mm 1 Disassembly and assembly Yes of case Frequency counter 4 digits 50 khz or ab...

Page 258: ...1 Repair NO Table 6 4 Oil Grease and Chemicals Name Standard O ty Use Commercial Iyavailable Flux remover 1 YES Instantaneous cooling agent 1 SOLDERING YES Alcohol YES Silicon lock 6 3 Soldering Inaduertant soldering of delicate component can cause component damage Carefully read and fllow the reccauting in Section 6 2 1 for component removal and soldering to safeguard the Maple computer s circuit...

Page 259: ... of parts 7 When soldering or removing flat package IC s use a special soldering iron and rapidly carry out the work When installing an IC place some solder on the pattern then place the IC on the pattern taking care not to bend its lead pins Quickly solder it with a soldering iron When placing the IC it may be fixed with a little amount of thread tightener or adhesive 8 When removing a chip compo...

Page 260: ...arts Q Proper CD Proper CD Do not allow the part to contact the board x X As a rule do not Lead wire must not bend the lead wire be too long Fig 6 3 Fig 6 4 Install the part in parallel with the surface of the board The limit of slanting angle is 15 CD Do not install the part too far from the surface of the board to prevent it from short circuiting other parts 6 5 ...

Page 261: ...lowing instances The copper foil in the through hole has come off The land has come off The print pattern has come off The board has been burned The board is cracked England drawing Treatment after the repair After repairing soldering the parts treat them according to the following procedure Remove all the flux from the soldered por tion with a brush etc Clean the patterns which you have touched C...

Page 262: ...a small amount of silicon lock on the variable re sistor as shown in Fig 6 8 Care must be used to keep the driver groove free from the lock agent 6 4 2 Screw Locking After any circuit board is replaced or any micro cassette tape drive azimuth adjustment is made apply a small amount of screw lock agent on the fixing screws or the azimuth ad justment screw as shown in Fig 6 9 6 4 3 Ensuring an FPC C...

Page 263: ...as a current limiting feature adjust it so that it works above 500 mA Adjust the voltage output to 5 0V and make sure that the computer is off before applying the regulator output to the computer If a higher voltage is inadvertently applied circuit com ponents may be damaged Press the INITIAL RESET switch once and then set the computer POWER switch ON 2 Voltages Low voltage detection level Lower t...

Page 264: ...serial interface 110 mA 4 Operating ROM capsule 90mA With two 27128s 5 Operating speaker 35mA At max sound level 6 Power off 45 C or above 1400 1A V e depend ng on the tempe atu 7 Power off 25 C 45 C 6OOl1A detected by thermistor TH 1 8 Power off below 25 C 3OOl1A 9 Power on idle 55 mA 6 5 2 Test Points 11 test points are provided on the MAPLE board which allow easy access to the VB supply line an...

Page 265: ...rocassette tape read data signal 4 9M Clock signal halved from the primary frequency of 9 8304 MHz which is used as the control clock signal for the LCD controller SED1320 MRG Issued from main CPU when D RAM memory is read written or refreshed SP Microcassette tape read data used as an output to the speaker CL2 Keyboard Scanning clock signal Adjust the pulse cycle to 11 5 to 12 5 ms 6 5 3 Variable...

Page 266: ...nd Switch Setting paying attention to the following J1 The J1 setting varies depending on the type of main CPU uPD 70008 Examine the main CPU chip 4A on the new board before setting J 1 J5 Use the same setting as the old board A or B If a different terminal is wired ghost dis plays may appear on the LCD panel J2 and J4 Use the same settings as on the old board The user may use other than the stan ...

Page 267: ... state and the tape should be loaded Press PF3 and PF4 respectively when stopping and rewinding the tape Table 6 8 Test Cassette Tape Routine Key Name of operation Description ISHIFTI IPF21 MOUNT Store the directory on the tape in the memory ISHIFTI IPF11 REMOVE Write the directory stored in the memory on the tape ISHIFTI IPF31 DIRINIT Initialize the directory on the tape IPF41 REWIND Rewind the t...

Page 268: ...crocassette drive shown in Fig 6 16 2 Connect the jack connector to the external speaker interface SP OUT 3 Connect the probe of the oscilloscope to the lead wire of the connector as shown in Fig 6 17 Azimuth hole cover adjustment screw below Fig 6 16 Fig 6 17 If the jack connector is not available solder two lead wires from the MAP MC board CN 1 con nector pins 3 and 5 as shown in Fig 6 18 Solder...

Page 269: ...lockwise 3 Lock the adjustment screw Set the oscilloscope near the following range Sweep DIV 200 J1S Reference Output signal of pin 7 of IC4 on MAP MC board The signal wave form should be about 200 mVP P as shown in Fig 6 19 G I I t __1l 1l t t___t__f_ t Fig 6 19 6 6 3 Tape Speed 2 4 cm s Make sure by using the AZIMUTH test tape that the output is within a range of 3 kHz 15 Hz as directly measured...

Page 270: ...n barcode reader and make sure that the patterns shown in Fig 6 21 can be read with the BARCODE CHECK test program 111111111111 1111111 I II 5 5 5 5 555 5 111111111111 1111111 III 5 5 5 5 5 5 55 111111111111 1111111111 II 5 5 55 5 5 55 Fig 6 21 6 15 ...

Page 271: ...ay GAH40M 7 17 7 6 Gate Array GAH40S 7 29 7 7 A D Converter uPD7001 7 34 7 8 Serial Controller 82C51 7 36 7 9 SED1120 LCDdriver 7 39 7 10 SED1130 LCD driver 7 44 7 11 LCD V RAM ControllerSED1320 7 50 7 12 D RAM uPD4265 7 57 7 13 V RAM 6117 7 61 7 14 Other ICs 7 64 7 15 Circuit Schematic Diagrams And Component Layout Diagrams 7 67 ...

Page 272: ... block diagram of the main CPU Registers consist of general purpose registers accumulator registers and flag registers Block diagram Accumulator and Flag Registers r v INSTRUCTION DECODE 13 CPU AND SYSTEM CONTROL SIGNALS CPU CONTROL INST REG CPU CONTROL iii 5V GND p 7 1 2 Functions of Major Registers 1 Program counter PC 16 bits Holds address of next instruction 2 Stack pointer SP 16 bits r Interr...

Page 273: ...CPU cannot be used because it is always pulled up by resistor R94 Therefore only the maskable interrupt INTR line is valid in this machine The interrupt function operates in one of the following three modes Mode 0 Executes the instruction normally RST or CALL read in MI mode condition after reset Mode 1 Saves the content of the program counter and automatically causes a branch to 0038H Mode 2 Exec...

Page 274: ... outputs a 30 40 Address Bus active high memory address or I O device number It outputs the lower 7 bit D RAM address for memory refresh 7 10 DBO 15 Tri state input An 8 bit data bus which is used for data 12 15 Data Bus and output transfer between memory or an I O device active high and main CPU 27 Ml Output A signal which indicates that the starting Machine active low machine cycle is the OP cod...

Page 275: ...I O device or memory is put on the data bus in synch ronization with this signal 28 RF Output This signal indicates during MI cycle that Refresh active low the dynamic RAM refresh address is output onto the lower seven bit lines of the address bus Dynamic RAM reads the refresh address using the MREO signal which is output toge ther with the RFSH signal 18 HALT Output This signal indicates that CPU...

Page 276: ...nterrupt is enabled or not The NMI signal has a priority over the INT signal 26 RS Input Resets CPU when active Reset active low 25 BURO Input When active this signal causes CPU to force Bus Request active low the address bus AO 15 data bus 00 7 and tri state system control terminals MREO IORO RD and WD in the high impedance state freeing the external buses for another device The BUSRO signal has ...

Page 277: ...nd sleep modes unique to 6303 are not used RES ROM IRQ 4K NMI E EXTAL RAM XTAL 128 Fig 7 26303 Slave CPU Functional Block Diagram Table 7 2 This computer uses a crystal oscillator for a 2 4576 MHz clock signal The slave CPU oper ates with the 614 4 kHz system clock signal which is internally quartered from the primary frequency of 2 4576 MHz The table opposite shows the port assignment 7 6 Port Po...

Page 278: ...TAL 2 4576 MHz 16 P13 In Microcassette tape head Unused reserved for non 4 NMI In load unload switch maskable interrupt input 17 P14 In Serial interface PIN signal 5 INTR In Interrupt request 18 P15 Out Serial interface POUT signal 6 RS In Reset signal 19 P16 Out Speaker output Unused reserved for Stand 7 STB In by signal input 20 P16 Out Speaker power on off 8 P20 In Microcassette tape read data ...

Page 279: ...ress bus Out 36 DA1 In Data address bus Out 31 DA6 In Data address bus Out 37 DAO In Data address bus Out 32 DA5 In Data address bus Out 38 Out R W Read Write 33 DA4 In Data address bus Out 39 AS Out Address strobe 34 DA3 In Data address bus Out 40 E Out ENABLE 35 DA2 In Data address bus Out 7 8 ...

Page 280: ...ervices The sub CPU exchanges data with the main CPU in a bit serial fashion via the gate array GAH40M Fig 7 3 is a functional block diagram of the sub CPU Table 7 4 lists the terminal sig nals and summarizes their functions Xl X2 COUNT CLOCK GENERATOR Cl CLOCK CONTROL PROGRAM MEMORY 2048 x 8 BITS 7507 4096 x 8 BITS 7508 SYSTEM CLOCK GENERATOR Cll Cl2 STANDBY CONTROL INSTRUCTION DECODER I I I VDD ...

Page 281: ...I Voo 20 21 CL2 Table 7 4 7508 SUB CPU Pin Assignments Pin No Signal Name In Out Function 1 x2 In Unused 2 P20 Out GAH40M SIOR access control H 7508 L Main CPU 3 P21 Out A D converter 7001 Chip Select mode switching between address data and A D conversion 4 P22 Out Ready signal 5 P23 Out A D converter 7001 power on off 6 P10 In Key return 0 7 P11 In Key return 1 8 P12 In Key return 2 9 P13 In Key ...

Page 282: ...A D con version data main CPU command read 25 SO Out Serial data output 26 SI In Serial data output 27 P60 In RESET switch 28 P61 In Charge start detection 29 P62 In Analog interface trigger input 30 P63 In Test point 31 P50 In Key return 4 32 P51 In Key return 5 33 P52 In Key return 6 34 P53 In Key return 7 35 P40 Out Reset signal initializes main CPU and slave CPU etc via GAH40 36 P41 Out Charge...

Page 283: ...of clock frequency Fig 7 4 shows an internal block of diagram of the GAH40D BANK IPL ROM AB15 CONTROL BANKO RO I 4 n RAS CAS WE Generating O RAM MREQ circuit BK2 9 8MHz Frequency divisor 1 2 1 1 4 11 9800 II 4 9M 2 45M 1K OW OCAS Fig 7 4 The BANK 0 1 signal is provided from the gate array GAH40M The main CPU sends this signal by writing bit 0 to I O address 00 0 bank 0 1 bank 1 BK2 signal is provi...

Page 284: ...C Not used 2 N C Not used 3 AB12 In Address bus 12 4 N C Not used 5 AB6 In Address bus 6 6 AB13 In Address bus 13 7 AB5 In Address bus 5 8 RST In Reset input from sub CPU 7508 Whole reset signal RSQ is generated from this signal 9 DRA2 Out DRAM address 2 10 10 ORA 1 Out DRAM address 1 9 11 AB14 In Address bus 14 12 G Ground 7 13 ...

Page 285: ...N C Not used 24 N C Not used 25 RD In Read signal 26 CSROM Out IPL ROM chip select signal 27 MR Out Memory read signal 28 Z INT Out Interrupt request signal to main CPU 29 Z RF In Refresh signal from main CPU 30 VC Circuit voltage 5V 31 HLTA In Halt signal 32 M1 In Indicates that main CPU is in machine cycle 1 opcode fetch 33 MRQ In Memory request signal 34 RSO Out System reset signal resets the w...

Page 286: ...SED1320 49 9 8 M In Clock input of 9 8404 MHz 50 2 45 M Out Clock output by dividing 9 8 MHz clock into four Clock for main CPU 51 1KC Out Clock output by dividing 32 KHz clock to 32 Clock for sub CPU 7508 52 TEST In Test terminal Normally kept low 53 OFF In Initializes signal for the whole internal cir cuit At high level initializes all FFs Hold 4 9 M 2 45 M CS ROM RD and Z INT at high le vel and...

Page 287: ...N C Not used 61 N C Not used 62 N C Not used 63 N C Not used 64 BK2 In DRAM select signal from option unit 65 VC Circuit voltage 5V 66 AB10 In Address bus 10 67 AB9 In Address bus 9 68 AB8 In Address bus 8 69 AB 11 In Address bus 11 70 AB 7 In Address bus 7 7 16 ...

Page 288: ...register A select line 7 Ii j II U II II I L v I Ql OJ 0 r c 20 C Ql Era 04W 8 I Interrupt vectoring 4 jlI Interrupt priority IIr Interrupt signal I Input capture 0 register J Vl J Ql 4 jlI II ra c Vl 04R r1 Free running counter Clock INTO 7508 614 4 KHz INT1 82C51 INT2 RS 232C DCD INT2 6303 INT5 EXT Fig 7 5 Control register f 0 r V Ql Qi en RXC TXC As shown in Fig 7 5 this gate array includes the...

Page 289: ...CR2 1 BCKO down Barcode mode select 0 timer 1 ICR1 BANKO Bank switching 0 ICRO 01 CMDR 01 ICRH C 7 7 ICR15 6 6 ICR14 5 5 ICR13 4 4 ICR12 3 3 ICR11 2 1 reset OVF Pulse timer 2 ICR10 1 1 reset RDYSIOFF Pulse SIO 1 ICR9 0 1 set RDYSIOFF Pulse SIO 0 ICR8 02 CTLR2 02 ICRL B 7 7 ICR7 6 6 ICR6 AUX External auxiliary output 5 ICR5 CD INHRS Inhibit RS 232C RS232 4 ICR4 SWRS RS 232C switch RS232 3 ICR3 CD L...

Page 290: ...303 6303 interrupt 1 IER1 INT 82C51 enable CD INT 1 lNT 82C51 82C51 interrupt 0 IERO lNT 7508 enable INTO lNT7508 7508 interrupt 05 05 STR 7 6 5 4 3 RDYSIO SIO ready SIO CD RDY ready SIO CD BRDT Barcode reader data timer 0 BANKO BANKO 06 SIOR 06 SIOR 7 SI07 7 SIO 7 6 SI06 6 SIO 6 5 SIO 5 5 SIO 5 4 SI04 4 SI04 3 SI03 3 SI03 2 SI02 2 SI02 1 SIO 1 1 SIO 1 0 SIOO 0 SIOO 07 07 During interrupt 1 1 1 1 ...

Page 291: ...s etc r v I l l cs 82C51 OC OE I ll I _ CS SED1320 AB7 00 01 To Address decoder 02 internal AB3 03 registers AB2 04 AB 1 ABO 05 06 RD I IOR 10RQ IOW WR RSDLY RS Fig 7 6 As shown in Figure 7 6 the main CPU can directly select internal registers via four address lines The CS signals of the 82C51 and SED1320 are also controlled by the I O address decoder via this registers 7 20 ...

Page 292: ... IER5 ISR5 external expansion board OVF Inside FRC overflow 1 111 1000 IER4 ISR4 lCF Inside ICR bar code trigger 11110110 IER3 ISR3 lNT6303 External pin request from 11110100 IER2 ISR2 6303 lNT82C51 External pin request 11110010 IER1 ISR1 from 82C51 lNT7508 External pin request from 11110000 IERO ISRO 7508 Address 04 W 0 Interrupt acknowledge A INT4 INT3 register I ER OF I r It r Interrupt priorit...

Page 293: ...I I OVF I 7 ICR H FRC H ck Data bus I ICR L I FRC L ck I OO W Fig 7 8 r RXC 0 u OJ a CJ TXC SWBCD control register selects baud rate i Barcode data When reading the content of FRC it is necessary to latch the content to ICR Input Capture Regis ter by reading address OOH Because the counter consists of 16 bits address OOH low order 8 bits and OIH high order 8 bits must be read separately Bits 1 and...

Page 294: ...t it means that the main CPU can access SIOA When it is reset it means that an interrupt signal is sent to the 7508 and the com mand set at SIOR is read by the 7508 The internal flip flop is controlled by bits 0 and 1 of ad dress OIH After the R W operation to from SIOR is completed the set status must be changed by writing to address OIH Table 7 8 Address OIH Reset The main CPU sets a command to ...

Page 295: ...d in order to inhibit output INHRS I 8V 1 _ voltage on the line during saturation time 8V 1 Bank switch 8VOUTPUT j REV A Fig 7 10 The address space of the main CPU can be changed using bit 0 of I O address OOH as shown be low OOH bit 0 OFF Bank 0 ROM RAM OOOOH 8000H FFFH OOH bit 0 ON Bank 1 I RAM I RAM I Fig 7 11 LED display ON OFF operation of shift mode LED on the keyboard is controlled using bi...

Page 296: ...ta bus 1 3 IR Out Indicates that data is being output according to main CPU instruction RS 232C main CPU 4 DBO In Out Data bus 0 5 DB2 In Out Data bus 2 6 CSOE Out SED1320 chip select signal 7 RS In Reset input Supplied from GAH40D 8 IW Out Indicates that data is being input according to main CPU instruction main CPU RS 232C 9 N C Not used 10 TXC Out Baud rate control clock for RS 232C 7 25 ...

Page 297: ... Out Serial data output to sub CPU 7508 18 S INT Out Interrupt signal to main CPU Gives an inter rupt via GAH40D Z INT signal 19 DB5 In Out Data bus 5 20 DB3 In Out Data bus 3 21 N C Not used 22 N C Not used 23 N C Not used 24 N C Not used 25 N C Not used 26 SWRS Out Switching signal for RS 232C power supply 27 INHRS Out Controls output voltage during power satura tion time of RS 232C 28 OFF In Po...

Page 298: ...NTS Out Interrupt signal to sub CPU 7508 42 ABO In Address bus 0 43 RDY In Ready signal of sub CPU 44 LED 2 Out Lamp control signal of LED on keyboard lowest of the three 45 AB 7 In Address bus 7 46 LED 1 Out Lamp control signal of LED on keyboard highest of the three 47 LEDO Out Lamp control signal of LED on keyboard center of the three 48 IORO In Main CPU in MI cycle Request to output in terrupt...

Page 299: ...In Out Function 54 N C Not used 55 N C Not used 56 DB4 In Out Data bus 4 57 AB 7 In Address bus 27 58 DB 7 In Out Data bus 59 2 45 In 2 45 MHz clock on which timer and baud rate generator are based 60 VC Circuit voltage 5V 7 28 ...

Page 300: ... ROM interface Figs 7 12 through 7 14 are functional block diagrams of these blocks 1 Address decoder block AB15 14 ASRW E ADB7 O IROO r r L 2 P ROM interface block 5V GAH40S Data bus c a CJ Address decoder IlPROM J address register lPROM rl data buffer Interrupt r1 ICounter 11 lcommand mask resister J Counter input sampler I CNTR MT Fig 7 12 Address decoder block diagram PROM l PROM 2 PROM nterfa...

Page 301: ...WS S R CBAC C DTHEW P t l JI I I JI JI JI GAH40S E piing Sam clock signal D FAST S I W STOPCNT I P I R 17 CMD 0 1 1 RDP2 1 I I r I 1 1 1 CNTH CNTL CNTR I 6 1 I 6 1 Sampler circuit Ul t I J J J I 1 Counter I I 5 bit I Counter 8 bit r Fig 7 14 Microcassette Tape Drive Interface Block Diagram 7 30 Speaker P13 P12 P11 P10 P21 P20 6303 ...

Page 302: ... 12 Out PROM address 12 2 PRA 14 Out PROM address 14 3 PRA 7 Out PROM address 7 4 PRA 13 Out PROM address 13 5 PRA6 Out PROM address 6 6 PRA8 Out PROM address 8 7 PRA 11 Out PROM address 11 8 PRA4 Out PROM address 4 9 PRA9 Out PROM address 9 10 PRA5 Out PROM address 5 11 PRA 10 Out PROM address 10 12 PRA3 Out PROM address 3 13 PRA2 Out PROM address 2 7 31 ...

Page 303: ...control signal A 27 MTDB Out Microcassette drive motor control signal B 28 MTDC Out Microcassette drive motor control signal C 29 G Ground 30 N C Not used 31 SWMCT Out Microcassette power switch 32 CNTR In Counter signal from microcassette 33 RDMC In Microcassette read data 34 CSLV Out SED1320 VRAM chip select signal Low le vel when addresses 8000 to BFFF are speci fied 35 N C Not used 36 CSLC Out...

Page 304: ...ddress data bus 3 48 DA2 In Out Slave CPU address data bus 2 49 E In Enable signal from slave CPU 6303 50 N C Not used 51 SWPR Out PROM power switch 52 TEST Test terminal Normally kept low 53 R W In Read write signal from slave CPU 6303 54 SINT In Interrupt signal from SED 1320 55 AS Out Address strobe signal from slave CPU 6303 56 PRD Out AND output from RDMC input and SMMC Outputs RDMC input to ...

Page 305: ...gns the analog input channels for battery voltage sensing temperature sensing barcode data input and external analog signal input Fig 7 15 is a functional block diagram and Fig 7 16 outlines the timing relationships among the operating signals Timing chart CS SO EOC SCK SI VDD DL SI SCK SO EOC Analog input channels o0 1 20 1 plexer 30 1 Reference input Analog 0 GND 9 bit shift register 0 0 CS I QC...

Page 306: ...read at the rising edge of the SCK signal 4 Serial Clock SCK In Controls the shift operation of the 9 bit inter face shift register 6 Chip Select CS In Controls uPD7001 s internal modes When CS is high A D conversion mode When CS is low Interface mode Dl SI SCK and SO etc have been strobed with CS All the terminals are disabled while CS is high 7 Clock Clo For connection of clock oscillation CR 8 ...

Page 307: ... I control I I Receive control I I L ______________ Fig 7 17 82C51 Serial Controller Block Diagram L L TXD RS 232C TXD Option TXRDY TXE Not used TXC GAH40M RXD RS 232C RXD Option RXRDY RXC SYNDET BD Not used The signals to the RS 232C interface are converted to the 8V RS 232C levels between 82C51 and the interface The Carrier Detect CD signal which is not included in the above block dia gram is co...

Page 308: ... OTR RTS OSR RESET ClK TxO Tx EMPTY CTS SYNOET 80 Tx RO Table 7 12 82CS1 Pin Assignments Pin No Signal Name Signal direction Meaning 1 D2 In Out Data bus 2 2 D3 In Out Data bus 3 3 RXD In Receive data from RS 232C interface or op tionl unit 4 GND Circuit ground 5 D4 In Out Data bus 4 6 D5 In Out Data bus 5 7 D6 In Out Data bus 6 8 D7 In Out Data bus 7 9 TXC In Out Data bus 7 10 WR In Transmitter c...

Page 309: ... provid ing full duplex communications 15 N C Not used 16 N C Not used 17 CTS In Clear to send 18 N C Not used 19 TXD Out Transmit data 20 ClK In 2 45M Hz clock 21 RS In Reset 22 DSR In Data set ready 23 RTS Out Request to send 24 DTR Out Data terminal ready 25 RXC In Receiver clock 26 VC In Circuit voltage 5V 27 DO Data 0 28 D1 Data 1 7 38 ...

Page 310: ...ve signals to 64 segments The internal diagram is shown in Fig 7 18 The drive level voltage may vary according to data received via DINs 0 to 3 VL5 VL3 VL2 VLG VDD DINO DINl DIN2 DIN3 XSCL FR LP XECL EI EO SEG SEG 65 t t LCD DRIVER LEVEL SHIFT EX OR LATCH t SHIFT REGISTER r 0 I w L L L L co l t VOLTAGE CONTROL a z r r I ENABLE CONTROL Fig 7 18 7 39 ...

Page 311: ...25 Out LCD drive segment output 25 4 S24 Out LCD drive segment output 24 5 S23 Out LCD drive segment output 23 6 S22 Out LCD drive segment output 22 7 S21 Out LCD drive segment output 21 8 S20 Out LCD drive segment output 20 9 S19 Out LCD drive segment output 19 10 S18 Out LCD drive segment output 18 11 S17 Out LCD drive segment output 17 12 S16 Out LCD drive segment output 16 13 S15 Out LCD drive...

Page 312: ...ive segment output 5 24 S4 Out LCD drive segment output 4 25 S3 Out LCD drive segment output 3 26 S2 Out LCD drive segment output 2 27 S1 Out LCD drive segment output 1 28 SO Out LCD drive segment output 0 29 EO Not used 30 03 In Serial data 3 31 02 In Serial data 2 32 01 In Serial data 1 33 DO In Serial data 0 34 XSCL In Transmission clock signal input terminal 35 LP Latch pulse 36 FR Frame signa...

Page 313: ...tput 47 53 S48 Out LCD drive segment output 48 54 S49 Out LCD drive segment output 49 55 S50 Out LCD drive segment output 50 56 S51 Out LCD drive segment output 51 57 S52 Out LCD drive segment output 52 58 S53 Out LCD drive segment output 53 59 S54 Out LCD drive segment output 54 60 S55 Out LCD drive segment output 55 61 S56 Out LCD drive segment output 56 62 S57 Out LCD drive segment output 57 63...

Page 314: ...ound 73 VDD In 5V Logic circuit voltage supply 74 TEST Unused 75 E 1 In Enable input corresponding to Chip Select 76 XECL In Enable transfer clock signal 77 S31 In LCD drive segment output 31 78 S30 In LCD drive segment output 30 79 S29 In LCD drive segment output 29 80 S28 In LCD drive segment output 28 7 43 ...

Page 315: ...ovides drive signals for the 64 horizontal lines Y driver COMO COM 63 Not used DOUT VL5 VL4 VL3 VR2 VR1 I I I C r VL2 0 VL 1I VLGil VDD DIN FR LP YSCL SPU YDIS 0 f OUTPUT LL BUFFER INPUT 1 1 BUFFER LCD DRIVER 64 Bit LEVEL SHIFT 64 Bit EX OR 64 Bit LATCH 64 Bit T SHIFT REGISTER 64 Bit f VOLTAGE CONTROL f j Fig_ 7 19 7 44 ...

Page 316: ...ponding to these data are output Data transfer timing is shown in Fig 7 20 Approx 285 I1sec YSCL 1 DIN D63 X D64 X DO LP 1 n n SPUI FR ___f 16 64 msec 260 I1sec x 64 Fig 7 20 When a YSCL signal is output DIN is included in the internal shift register an LP signal latches the content of the shift register and the latched data is output on the Y drive line 7 45 ...

Page 317: ...rive common output 29 4 COM 28 Out LCD drive common output 28 5 COM 27 Out LCD drive common output 27 6 COM 26 Out LCD drive common output 26 7 COM25 Out LCD drive common output 25 8 COM 24 Out LCD drive common output 24 9 COM 23 Out LCD drive common output 23 10 COM 22 Out LCD drive common output 22 11 COM 21 Out LCD drive common output 21 12 COM 20 Out LCD drive common output 20 13 COM 19 Out LC...

Page 318: ...ut 8 25 COM7 Out LCD drive common output 7 26 COM6 Out LCD drive common output 6 27 COM 5 Out LCD drive common output 5 28 COM4 Out LCD drive common output 4 29 COM 3 Out LCD drive common output 3 30 COM2 Out LCD drive common output 2 31 COM 1 Out LCD drive common output 1 32 COMO Out LCD drive common output 0 33 COM 32 Out LCD drive common output 32 34 COM 33 Out LCD drive common output 33 35 COM...

Page 319: ... 51 OUT LCD drive common output 51 53 COM 52 OUT LCD drive common output 52 54 COM 53 Out LCD drive common output 53 55 COM 54 Out LCD drive common output 54 56 COM 55 Out LCD drive common output 55 57 COM 56 Out LCD drive common output 56 58 COM 57 Out LCD drive common output 57 59 COM 58 Out LCD drive common output 58 60 COM 59 Out LCD drive common output 59 61 COM 60 Out LCD drive common output...

Page 320: ...supply 75 YSPU In Low impedance drive input Normally high When low the externally connected resistor parallels the internal impedance lowering the total impedance through which the line can be driven at the divided LCD voltages VL1 5 76 YDIN In Serial data input 77 YSCL In Transmission clock input 78 YDIS In Display control input 79 FR In Frame signal 80 LP In Latch pulse 7 49 ...

Page 321: ...on capability for LCD display Fig 7 21 is a functional block diagram of SED1320 External 4 9M ____ 1 2 dividerI clock signal GAH40D circuit to 6303 PDO 7 PAO PRD l PVVR DMA X V count ddress V clock comman signal Character generator I r r l I I L r r LAO 12 FR LP LVVE LCD data XSCL XDO 3 VSCL XECL VSPU ADO 7 1 R VV Decoder Data AS I E I I I A8 A12 DO 7 Address LCSE1 3 AO 12 Fig 7 21 SED1320 Gate Ar...

Page 322: ...ed character set is determined by the DIP SW4 setting which anyone of the international character sets The switch is read at initialization 7 11 2 Communications Between Main And Slave CPUs When the main CPU sends a command or data to the PDIR register the SINT signal interrupts the slave CPU via the gate array GAH40S lNTR signal The slave CPU reads the command data by setting the interrupt mask r...

Page 323: ... causes an inter rupt to slave CPU 6303 via GAH40S SINT becomes low when command is set in PDIR register by main CPU SINT becomes high when the slave CPU reads CSR register 3 SCS In System chip select and V RAM select signal 4 SCS1 In System chip select Register select signal in SED1320 5 SE In System enable Pulse at 1 63 lsec interval 6 SAS In System address strobe Latches low order address at po...

Page 324: ... synchronizing to SE sig nals 18 SA 10 In System slave CPU 6303 address data bus 10 Data is input output synchronizing to SE sig nals 19 SA 11 In System slave CPU 6303 address data bus 11 Data is input output synchronizing to SE sig nals 20 SA 12 In System slave CPU 6303 address data bus 12 Data is input output synchronizing to SE sig nals 21 N C Not used 22 PCS In Port chip select Provided from G...

Page 325: ...O 5 In Out Local data for V RAM 5 40 LO 6 In Out Local data for V RAM 6 41 LO 7 In Out Local data for V RAM 7 42 LAO Out Local address for V RAM 0 43 LA 1 Out Local address for V RAM 1 44 LA2 Out Local address for V RAM 2 45 LA3 Out Local address for V RAM 3 46 LA4 Out Local address for V RAM 4 47 LA5 Out Local address for V RAM 5 48 LA6 Out Local address for V RAM 6 49 LA 7 Out Local address for ...

Page 326: ...x 280 f1 sec 62 YDIS Out Y display Displayed on LCD when HIGH 63 FR Out Frame signal Connected to XY driver 64 LP Out Latch pulse signal Connected to XY driver Latches data at falling edge Output at an interval of approx 280 f1 sec 65 XSCL Out X shift clock Shifts X data 66 XDO Out X data 0 X line data for LCD display 67 XD 1 Out X data 1 X line data for LCD display 68 XD2 Out X data 2 X line data...

Page 327: ...nal Name In Out Function 76 LCKO Out Local clock 0 External clock for slave CPU 6303 2 45 MHz obtained by dividing LOSC into two frequencies 77 G Circuit ground 78 G Circuit ground 79 N C Not used 80 N C Not used 7 56 ...

Page 328: ...ng power consumption Those modes are automatically selected depending on sensed ambient temperature Figs 7 22 and 7 23 respectively show the Timing relationships among major control signals in the read and write cycles Read cycle RAS CAS Address x ROW 0 COLUMN X X ROW x WE DO Valid read data Fig 7 22 DRAM Read Cycle Operation Timing Write cycle RAS __________________________ CAS ______________ X A...

Page 329: ... TO 7DOC RAS V1H J VIL XXXXXXXY _ RFSH VIH VIL I _ _ _ _ _ J 1 _____ 7 SELF REFRESH CYCLE DOC TO 45 C RAS V1H J VIL RFSH VIH VIL WE V1H VIL ______7 SELF REFRESH CYCLE DOC TO 25 C RAS V H J VIL RFSH VIH VIL CAS VDD GND WE VDD GND X __ X Fig 7 27 7 58 REV A ...

Page 330: ...ESH CYCLE CAS VIH ______________ VIL ADDRESSES I RFSH VIH _ _ _ _ _ _ _ VIL _ ff DOUT ______ V a lid da t a o ut p ut _____ Fig 7 28 HIDDEN REFRESH RAS VIH VIL CAS VIH VIL ADDRESSES I lS I ROW XCOL DOUT __________________ Fig 7 29 7 59 ...

Page 331: ...4 13 12 11 10 9 Vss CAS oOUT As A3 AI As A7 Table 7 16 tlPD4265 Pin Assignments Pin No Signal Name In Out Function 1 RF In Refresh 2 DI In Data IN 3 W In Write enable 4 RAS In ROW address strobe 5 6 7 AO A2 In Address 8 VDD In 5V circuit voltage 9 13 A3 A 7 In Address 14 DO Out Data out 15 CAS In Column Address strobe 16 VSS In Ground 7 60 REV A ...

Page 332: ...ta if power is turned off The RAMs are accessed via the slave CPU 6303 A functional block diagram of V RAM circuitry is illustrated in Fig 7 30 Fig 7 30 is a functional block diagram of 611 7 Al A2 Vcc A3 j A4 Row Memory Matrix GND A5 Decoder 128 128 A6 r A7 I I 1 01 1 t Column I O CE2 Input Cplumn Decoder I I Data I I Control I I I I I I j I 1 02 l I I A7 AS A9 Al0 I I f t J 1 J CEl WE Fig 7 30 6...

Page 333: ...A3 A2 Al Ao I O 1 1 02 1 03 GNO 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vee As A9 WE CE2 A 10 CE 1 I Os 1 07 I Os 1 05 1 04 Table 7 17 6117PE Pin Assignments In Out Function In Address 7 In Address 6 In Address 5 In Address 4 In Address 3 In Address 2 In Address 1 In Address 0 In Out Data 0 In Out Data 1 In Out Data 2 Not used In Out Data 3 7 62 REV A ...

Page 334: ...ut Data 4 15 D5 In Out Data 5 16 D6 In Out Data 6 17 D7 In Out Data 7 18 CE 1 In Chip enable 1 19 AB10 In Address 10 20 CE 2 In Chip enable 2 21 WE In Low level Write High level Read 22 AB9 In Address 9 23 AB8 In Address 8 24 Vcc Circuit voltage 5V 7 63 ...

Page 335: ...2 13 I I I I I I I I r9 l I I I I L ___________________________ J 6 5 4 3 2 Pin 1 Vcc 7 GND 4093BP 13 12 II 10 9 8 r I I I I I I I I I I I I I I I I I I L _________________________________ J 2 3 4 5 6 4011UBP 8 9 10 II 12 13 r I I I I I I I I I I I I I I I I I I I I l I L____________ _____________ 6 5 4 3 2 Pin 7 Vss 14 VDD 7 64 ...

Page 336: ...ee 13 16 Unused 40H004 13 12 II 10 9 8 r t j t JI I CJ tJ CJj 2 3 4 5 6 Pin 7 GND 14 VDD TD62504 16 15 14 13 12 I I 10 I I r 1 I I I I I I I I I I I I 1 L _______________________________ J I 2 3 4 5 6 7 8 GNO Pin 9 Not used 7 65 ...

Page 337: ...REV A 40H386 Vee 48 4A 4Y 3Y 38 3A 1A 18 1Y 2Y 2A 28 GND Y A E8 B AB AB 7 66 ...

Page 338: ... 1 1 _ no 1 jg4 l ro r I I __ l I i O K r QO 60 R3 IDE 4 R65 11t32 r 5 2t l5 t 10K _ 7 518 4 NMI J 3K 0 G r moK _ _ _ O Pl7 fii t 9 t 9 Sf I st 7C ra 12111098 t t 121 76S4321Bt 01320 5 666666 Q060661 r H b t r r gt fe 23 1 0 D 4 2 1 5 67 q lOll 111 615 I eNS 16 LCD err ABO 7654 3 2 I 0 0 10 q II 7 6 5 32 I 0 52 I 4 75188 l 093BP 401lUBP 1 0 0 I JOK R72 fO 55 C2812 330P 34 27 47K 10 20 10K 1 4 7 K ...

Page 339: ...ROWN SW2 BROWN WEI H _0 OFGI FANGI _OFG2 FANGI LED E oRANGI 0 E BLUE r o HPM I RED HPM2 BLACK RI2 CB 220 IJj Q4 f 2S060IR RII 1 15K C9 r CIO Iir lfJ 0 M RED M BLACK l ______________________ ____________ R 3 3 nK _ l 22 R20 270K 2 R 22O Jl 2 1 R I0 25 K l j MAI53 r 2 P 1 n rf11220Pl 41 RMI4n __rlj il 1 3 1 lrt ovRPH PINK IC5 C28 47P 4069 14 V1 9 rt 7 R31 15K C29 T 1000P R27 2 10 10K C20 R21 CIB 3 I...

Page 340: ...I CN6 7 50 7 90 1 1 1 1 7 1 i 1 DA2 I eM iI I J j 2 0 l 49 840H 4 CNIO CN9 If z 0 ____I N z o 0 j 7 GIlD i L _ _ 4 l JMAPLE BOARD cfo 0 _ 2A 1 4A 40 LI_ __ 20 11 M2L 50 3 0 AA 55 ROllI 2 O ROtil I REV A N L_ on D o N MAP MC D UNIT Y2032020000 2___ N ID o BATI IBI H3YO 7 69 ...

Page 341: ...7I RI C R 10 C27 EB R37 C26 R9 EB R30 R42 B03 R36 R31 R24 C C23 R35 C td C 22 0 CJ C J C20 R40 R33 R22 R CffiR 06 15 I C26 0 2 R21 qJl7 I ff C2 50 HPM 01 6 4U j J3 0 R3 r J CI iii iii HSW Rq C J RI6 C13 a n 44 C RPHI I I I C34 R99 RI41 C D IT RII6 RI30 0 CD C J uLlD 0 G lc RL8 RI31 R129C J C30CJ O W C JC J u RI09 Rloa D 0 C31CJu w a R14 J Cl I R31 III 0 D R R6 C79 C LJ R51 R77 D EB RII2 0 n U W RI...

Page 342: ...J O I VLGp r CIS PINNO NAME 1 5EG27 t l J 16 3 25 4 24 5 23 6 22 7 21 8 9 19 10 18 J 1 17 I I HMI I t 1 n K 0 0 f lf lf Hfllf f iJiiJiV i XECL 4 X5CL FR 12 L P EJ DO 01 l 12 2QOJ SED 11 20 vooP VL EO TE5T70 VL2 VLJ VLS U _ _0 1 1 j I PINNOiNA E PINNQ NAME ANNO NAME 17 5EG11 33 OlNO 49 SEG44 16 10 34 XSCL 50 451 19 9 35 LP 51 46 20 8 36 FR 52 47 21 7 37 SEG32 53 48 t 3 54 49 39 34 55 50 L 4 40 35 _...

Page 343: ... XI X2 X3 X4 I l I I 24 I 124 I 24 I I C5 C6 7 RM2 I I C D a I 7 72 141 I I I 1 1 1 1 1 1 1 1 0 X5 X6 I I I 24 24 24 17 15 10 CNI 5 I 7 RMI I II UNIT Y20320400000 DEC 32V OI i I 1 l I X7 I 24 __ J I r I MAP LD Board II ...

Page 344: ...REV A A B C D E F G H T KEY NO t 2 t 27 42 56 3 t 4 27 I 42 I T 56 69 5 t 6 t D ex 7 0 0 0 0 0 0 t D ex 0 u 0 0 u u u z z Vl Vl Vl Vl Ll Ll 8 2 3 4 5 6 7 8 9 10 II 12 13 14 15 16 17 18 19 20 21 22 7 73 ...

Page 345: ...REV A 7 74 ...

Page 346: ...147 S G D6IS2 J 06 X2 f Ol 069UBP j J y 30 65 1 Wi CASI 7 2 f TEST I lr C R 9i5304M oR33 1 10M 56 6 16M 49 I P hOP C8 C6 741 1C04 CR 2 2 7 611 r 1enl 6 6 sf R35 t tt j 33K R 1M II 3 3 f r 0 5B 6 6 8 3 L 13 i 5B 1R20 1M 12 SB o R Q A 7C 7C RM2 2 E 3K 8 1411129 658 210 IIH STATU5 REA 3 to 7 8 3 LoI 8 H37L 8B 11 0 1 2 34567 S ell 6 I 6 m 1 0 1 C I Y12Sl r4 t 19IO r 9 i9 I Z02345678 8 O 2 RM 3C I RMs ...

Page 347: ...4 I RM2 1 20 1 RM4 CNI 49 DI 8A I J 10 L IS 40H 245 88 I I 20 II 10 244 20 I v IIIAP RF BOARD i i j lP04265lCS 0 0000 0 T I rv 20 j lPD4265lCS L 4OH374 1 1 0 0 0 4OH3S7 40H244 II 40HOOO 40H074 40HOoo 40H074 40H074 E B B D7 DB i De i 1 i J 1 MAP RF BOARD UNIT Y20420400000 IBI H3VO 0 o ...

Page 348: ...26 7 3 7214331 3 Telex 34714 EPSON FRANCE S A 114 Rue Marius Aufan 92300 Levallois Perret France Phone 1 758 77 00 Telex 614169 EPSON UK LTD Dorland House 388 High Road Wembley Middlesex HA9 6UH U K Phone 01 902 8892 Telex 8814169 EPSON ELECTRONICS SINGAPORE PTE LTD No 1 Maritime Square 02 19 World Trade Centre Singapore 0409 Phone 2786071 2 Telex 39536 EPSON ELECTRONICS TRADING LTD TAIWAN BRANCH ...

Page 349: ...EPSON Printed in Japan 84 09 3 ...

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