3. All interface conditions are based on TTL level. Both the rise and fall
times of each signal must be less than 0.2
4. Data transfer must not be carried out by ignoring the ACKNLG or BUSY
signal. (Data transfer to this printer can be carried out only after con-
firming the ACKNLG signal or when the level of the BUSY signal is
“LOW’.)
(4) Data transfer sequence
Fig. A2-1 shows the sequence for data transmission.
Fig. A2-1 Parallel Interface Timing
Relations among the ON LINE switch, SLCT IN signal, DC l/DC 3 code and inter-
face signals are shown in Table A2-2 below.
Table A2-2 Relations among ON:LINE. SLCT IN, DC1 /DC3 and Interface Signal
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Summary of Contents for MX-82
Page 1: ...M X 8 2 EPSON DOT MATRIX PRINTER Operation Manual MX MX 82 F T EPSON P8190027 2 ...
Page 80: ......
Page 89: ...Fig Al 1 Control Circuit Diagram ...
Page 91: ...9 X 2SD986 HI D H LFA 0 LFA LFC 0 LFD Fig A1 2 Driver Circuit Diagram 8 6 ...
Page 96: ...I Hex o I 2 3 4 I I No 5 617 8 9 A 6 c D I I S I l l Ic ...
Page 100: ...SPAIN 23 55 5c 50 78 7c 9 6 ...