Principles of Operation
Reset Circuit
The control circuits are initialized when the RESET signal is issued. The reset operation occurs
under these two conditions:
1. Power on reset
Immediately after the power is turned on,
VDC is rapidly generated. Because it takes a
moment for the voltage at
to reach
V, the voltage at the DISC terminal on the gate
array does not reach VDC until capacitor C24 is fully charged. A similar integration circuit
is provided in the gate array and further delays the output of the ROUT signal. This LOW
level is used as a reset signal.
2.
signal reset
The reset signal is also issued when the
signal is sent
the host computer.
Figure 6-25 shows the power on reset circuit.
RIN
DISC ROUT
I 15
Epson FX-870/1170
6-25