7: Memory Management Unit
7-16
EPSON
ARM720T CORE CPU MANUAL
7.5
Fault address and fault status registers
On an abort, the MMU places an encoded 4-bit value, FS[3:0], along with the 4-bit encoded
domain number, in the data FSR, and the MVA associated with the abort is latched into the
FAR. If an access violation simultaneously generates more than one source of abort, they are
encoded in the priority given in Table 7-9.
7.5.1
Fault Status
Table 7-9 describes the various access permissions and controls supported by the data MMU
and details how these are interpreted to generate faults.
Note:
Alignment faults can write either b0001 or b0011 into FS[3:0]. Invalid values in
domains [3:0] can occur because the fault is raised before a valid domain field has
been read from a page table descriptor. Any abort masked by the priority encoding
can be regenerated by fixing the primary abort and restarting the instruction.
Table 7-9 Priority encoding of fault status
Priority
Source
Size
Status
Domain
FAR
Highest
Alignment
-
b00x1
Invalid
MVA of access
causing abort
Translation
Section
Page
b0101
b0111
Invalid
Valid
MVA of access
causing abort
Domain
Section
Page
b1001
b1011
Valid
Valid
MVA of access
causing abort
Permission
Section
Page
b1101
b1111
Valid
Valid
MVA of access
causing abort
Lowest
External abort on noncachable
nonbufferable access or
noncachable bufferable read
Section
Page
b1000
b1010
Valid
Valid
MVA of access
causing abort
Summary of Contents for ARM720T Core cpu
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Page 13: ...Preface ...
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Page 19: ...1 Introduction ...
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Page 39: ...2 Programmer s Model ...
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Page 59: ...3 Configuration ...
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Page 71: ...4 Instruction and Data Cache ...
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Page 75: ...5 Write Buffer ...
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Page 79: ...6 The Bus Interface ...
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Page 95: ...7 Memory Management Unit ...
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Page 119: ...8 Coprocessor Interface ...
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Page 131: ...9 Debugging Your System ...
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Page 177: ...10 ETM Interface ...
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Page 199: ...Appendix A Signal Descriptions ...
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Page 209: ...Glossary ...
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Page 217: ...Index ...
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