EPOX EP-3VHA, User Manual

Page: 30 / 73

BIOS
Page 4-7
DRAM Clock/Drive Control
Current FSB Frequency: CPU clock frequency information. (No option/Display
only).
DRAM Clock : The item will synchronize/asynchronize DRAM clock operation.
Host CLK: Sets the memory to run at the same speed with the processor’s
front side bus. If you have CPU at 133MHz FSB & PC133 memory,
please use this selection.
HCLK+ 33M: Sets the memory to run at 33MHz faster than the processor’s
front side bus. We recommend to select this item while your CPU
is running at 100MHz FSB and memory is PC133 specification to
optimize your system performance.
HCLK - 33M: Sets the memory to run at 33MHz slower than the processor’s
front side bus. This selection is suggested to be used under CPU
at 133MHz FSB and PC100 memory configuration.
By SPD: SDRAM clock by SPD data.
4-3 Advanced Chipset Features
Choose the “CHIPSET FEATURES SETUP” in the CMOS SETUP UTILITY menu
to display following menu.
Figure 4: Chipset Features Setup