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EN63A0QI
Evaluation Board User Guide
Nov 2010
Page 6 of 9
D1
S2A
+
C14
VIN
TP27
J7
J6
J11
1206
1210
1210
1206
C1
FB1
C4
0
8
0
5
0
8
0
5
0
8
0
5
0805
0
8
0
5
0
8
0
5
C8
C9
R11
VFB
J2
1
2
3
J3
1
2
3
TP6
0
8
0
5
0805
J10
VOUT
M/S
ENA
J4
TP9
1
2
C3
TP15
TP14
R2
1206
C
2
VIN
PGND
ENA
M/S
POK
VOUT
PGND
C15
0
8
0
5
0805
C5
C6
R
8
R
7
R3
R
6
C7
AVIN
0402
0402
TP30
TP31
J1
1
2
3
R13
VFB
R14
V
F
B
R4
SEL
TP3
0
8
0
5
SEL
TP5
FADJ
XREF
0
8
0
5
0
8
0
5
R
5
TP21
TP22
TP32
0
8
0
5
SIN
SOUT
SCH 04696
PCB 04697
Provision for Implementing
Adaptive Voltage Scaling
0
4
0
2
1210
C10
C12
C11
C13
TP19
1
2
TP20
1
2
C16
R10
VIN
VOUT
R1
T
P
1
0
0
4
0
2
TP8
TP7
J5
1
3
5
2
4
6
8
7
D2
TP28
BF_IN
0
8
0
5
T
P
2
9
TP17
1
2
TP18
1
2
R9
TP11
U1
EN63A0Q
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
NC10
10
NC11
11
NC12
12
NC13
13
NC14
14
N
C
1
9
1
9
V
O
U
T
2
0
V
O
U
T
2
1
V
O
U
T
2
2
V
O
U
T
2
3
V
O
U
T
2
4
V
O
U
T
2
5
V
O
U
T
2
6
V
O
U
T
2
7
V
O
U
T
2
8
N
C
2
9
2
9
N
C
(S
W
)3
0
3
0
N
C
(S
W
)3
1
3
1
P
G
N
D
3
2
P
G
N
D
3
3
P
G
N
D
3
4
P
G
N
D
3
5
P
G
N
D
3
6
P
G
N
D
3
7
S_IN
56
PGND
55
VDDB
54
NC53
53
NC52
52
PVIN
51
PVIN
50
PVIN
49
PVIN
48
PVIN
47
PVIN
46
PVIN
45
PVIN
44
PVIN
43
N
C
7
6
7
6
N
C
7
5
7
5
N
C
7
4
7
4
N
C
7
3
7
3
N
C
7
2
7
2
N
C
(S
W
)7
1
7
1
N
C
(S
W
)7
0
7
0
E
N
_
P
B
6
9
F
Q
A
D
J
6
8
E
X
T
R
E
F
6
7
V
S
E
N
S
E
6
6
S
S
6
5
E
A
O
U
T
6
4
V
F
B
6
3
M
/S
6
2
A
G
N
D
6
1
A
V
IN
6
0
E
N
A
B
L
E
5
9
P
O
K
5
8
P
G
N
D
3
8
S
_
O
U
T
5
7
PVIN
42
PVIN
41
PVIN
40
PVIN
39
NC15
15
NC16
16
NC17
17
NC18
18
TP12
Short across R9
when all other
routing completed
TP4
TP1
VIN
TP23
TP2
TP16
T
P
2
4
TP25
TP13
TP26
U2
Figure 5: Evaluation Board Schematic