EN6337QI/EN6347QI
Evaluation Board User Guide
Nov 2010
Page 4 of 9
conducted at this point. The over current trip level, short circuit protection, under voltage
lock out thresholds, temperature coefficient of the output voltage may also be measured
in this configuration.
CAUTION: The maximum allowable VIN for this version of devices is 6.6V.
STEP 6A: Power Up/Down Behavior
– Remove ENA jumper and connect a pulse
generator (output disabled) signal to the clip-on test point below ENA and Ground. Set
the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to 10msec. and
duty cycle to 50%. Hook up oscilloscope probes to ENA, SS, POK and VOUT with clean
ground returns. Apply power to evaluation board. Enable pulse generator output.
Observe the SS capacitor and VOUT voltage ramps as ENA goes high and again as
ENA goes low. The device when powered down ramps down the output voltage in a
controlled manner before fully shutting down. The output voltage level when POK is
asserted /de-asserted as the device is powered up / down may be observed as well as
the clean output voltage ramp and POK signals.
STEP 7: External Clock Synchronization / Spread Spectrum Modes
: In order to
activate this mode, it may be necessary to a solder a SMA connector at J8. Alternately
the input clock signal leads may be directly soldered to the through holes of J8 as
shown below.
GND
Ext. Clock
Figure 3: SMA Connector for External Clock Input
Power down the device. Move ENA into disable position. Connect the clock signal as
just indicated. The clock signal should be clean and have a frequency in the range of
the nominal frequency
±
15%; amplitude 0 to 2.5 volts with a duty cycle between 20 and
80%. With SYNC signal disabled, power up the device and move ENA jumper to
Enabled position. The device is now powered up and outputting the desired voltage.
The device is switching at its free running frequency. The switching waveform may be
observed between test points SW and GND. Now enabling the SYNC signal will
automatically phase lock the internal switching frequency to the externally applied
frequency as long as the external clock parameters are within the specified range. To
observe phase-lock connect oscilloscope probes to the input clock as well as to the SW
test point. Phase lock range can be determined by sweeping the external clock
frequency up / down until the device just goes out of lock at the two extremes of its
range.
