Warning!
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is
released from reset. Violating this rule may damage the equipped MPSoC device, as well as other
devices on the XU1 SoC module.
3.2
Module Connector C Detection
Signal C_PRSNT# (pin C-167) must be connected to GND on the base board if the designed base board has
three connectors. Depending on the value of this pin, the FPGA banks routed to module connector C are
supplied with the voltages provided by the user (when C_PRSNT# is low) or with a default voltage of 1.8 V
(when C_PRSNT# is unconnected).
C_PRSNT# is equipped with a 4.7 k
Ω
pull-up resistor on the module.
3.3
Pull-Up During Configuration
The Pull-Up During Configuration signal (PUDC) is pulled to GND on the module; as PUDC is an active-low
signal, all FPGA I/Os will have the internal pull-up resistors enabled during device configuration.
If the application requires the pull-up during configuration to be disabled, this can be achieved by removing
R201 component and by mounting R228 - in this configuration the PUDC pin is connected to 1.8 V.
Figure 15 illustrates the configuration of the I/O signals during power-up. Figure 16 indicates the location of
the pull-up/pull-down resistors on the module PCB - lower right part on the bottom view drawing.
Figure 15: Pull-Up During Configuration (PUDC) and Power-on Reset Delay Override (PORSEL) - Revision 4 Modules
D-0000-428-001
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Version 13, 15.08.2019
