Hardware Manual: emSTAMP- emSBC-Argon (Rev1)
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The PHY LAN8720A is integrated on the CPU module so that an Ethernet Jack (with integrated
magnetics) may be directly connected to the modules Ethernet pins ETH_RDP/ETH_RDM and
ETH_TDP/ETH_TDM which are available at the castellated mounting holes of the module. An
appropriate 1:1 transformer with a 100nF capacitor to GND and a 3.3V supply at each center tap pin
must be added externally. Link or traffic indication signals for additional LEDs are not provided.
Module Pin
CPU Pin Name
Signal
Direction
(module view )
Termination
19
-
ETH_TDM
AO
20
-
ETH_TDP
AO
22
-
ETH_RDM
AI
23
-
ETH_RDP
AI
5.6
USB 2.0
The STM32MP157 contains two high-speed PHYs. The processor provides an USB 2.0 high-speed
host controller and an USB 2.0 OTG high-speed controller.
5.6.1
USB 2.0 Host
The STM32MP157 provides an USB 2.0 compliant host interface, supporting data transfers at low-
speed (1.2 Mbit/s), full-speed (12 Mbit/s) and high-speed (480Mbps).
The VBUS supply voltage is provided by the PMIC of the emSTAMP-Argon. Over-current protection
is done by the PMIC.
Module Pin
CPU Pin Name
Signal
Direction
(module view )
Termination
50
USB_DP1
USBH_HS1_DP
AI/O
51
USB_DM1
USBH_HS1_DM
AI/O
52
-
USBH VBUS
Power output
5.6.2
USB 2.0 OTG
The STM32MP157 provides an USB 2.0 compliant OTG interface, supporting data transfers at full-
speed (12 Mbit/s) and high-speed (480Mbps).
Module Pin
CPU Pin Name
Signal
Direction
(module view )
Termination
40
PA10
USB_OTG_HS_ID
I
41
-
USB_OTG VBUS
Power I/O
43
USB_DP2
USB_OTG_HS_DP
AI/O
44
USB_DM2
USB_OTG_HS_DM
AI/O
If the USB_OTG_HS_ID signal (PA10) is tied to GND (logical “0”) by an external device/connector,
the CPU module enters host mode. A floating ID signal places the CPU in device mode.
