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25

TF single on BTB connector: Connected to uSDHC2
On-board QSPI Flash: Connected to QSPI, 1.8V 64M bit QSPI flash, W25Q64FW

USDHC IO VOLTAGE

SELECTION For 

Manufacture Mode

0 - 3.3V

1 - 1.8V

BOOT_CFG[14]

SD Loopback Clock

Source Sel  (for SDR50

and SDR104 only)

'0' - through SD pad

'1' -  direct

BOOT_CFG[10]

BOOT_CFG[11]

BOOT_CFG[12]

BOOT_CFG[13]

BOOT_CFG[15]

4

0x470[15:8]

BOOT_CFG[8]

BOOT_CFG[9]

5

6

7

0

2

3

Port Select:

00 - uSDHC1

01 - uSDHC2

10 - uSDHC3

Power Cycle Enable

'0' - No power cycle

'1' - Enabled via 

Address

1

100 - QSPI

011 - NAND

Infinit-Loop

(Debug USE only)

0 - Disable

1 - Enable

010 - MMC/eMMC

001 - SD/eSD

SPI Addressing:

0 - 3-bytes (24-bit)

1 - 2-bytes (16-bit)

Port Select:

000 - eCSPI1

001 - eCSPI2

010 - eCSPI3

FLASH_TYPE

000-Device supports 3B read by default

001-Device supports 4B read by default

010-HyperFlash 1V8

011-HyperFlash 3V3

100-MXIC Octal DDR

Nand_Row_address_bytes:

00 - 3

01 - 2

10 - 4

11 - 5

Pages In Block:

00 - 128

01 - 64

10 - 32

11 - 256

110 - SPI NOR

0x470[15:8]

0x470[15:8]

Others - Reserved for future use

0x470[15:8]

0x470[15:8]

0x470[15:8]

0x470[15:8]

BOOT_CFG[4]

BOOT_CFG[5]

BOOT_CFG[7]

BOOT_CFG[6]

Reserved

BOOT_CFG[0]

BOOT_CFG[1]

BOOT_CFG[2]

BOOT_CFG[3]

BOOT_SEARCH_COUNT:

00 - 2

01 - 2

10 - 4

11 - 8

Bus Width:

000 - 1-bit

001 - 4-bit

010 - 8-bit

101 - 4-bit DDR (MMC 4.4)

110 - 8-bit DDR (MMC 4.4)

Else - reserved.

Fast Boot:

0 - Regular

1 - Fast Boot 

Bus Width:

0 - 1-bit

1 - 4-bit

Speed

000 - Normal/SDR12

001 - High/SDR25

010 - SDR50

011 - SDR104

101 - Reserved for DDR50

Others - Reserved 

Reserved

Toggle Mode 33MHz Preamble Delay, Read Latency:

'000' - 16 GPMICLK cycles.

'001' - 1 GPMICLK cycles.

'010' - 2 GPMICLK cycles.

'011' -  3 GPMICLK cycles.

'100' - 4 GPMICLK cycles.

'101' - 5 GPMICLK cycles.

'110' - 6 GPMICLK cycles.

'111' - 7 GPMICLK cycles.

'1111'- 15  GPMICLK cycles.

USDHC IO VOLTAGE

SELECTION For 

Normal Boot Mode

0 - 3.3V

1 - 1.8V

0x470[7:0]

0x470[7:0]

0x470[7:0]

0x470[7:0]

0x470[7:0]

Speed

00 - Normal

01 - High

10 - Reserved for HS200

11 - Reserved 

Reserved

Reserved

HOLD TIME:

00 - 500us

01 - 1ms

10 - 3ms

11 - 10ms

BT_TOGGLEMODE

Reserved

Reserved

FlexSPI FLASH Dummy Cycle

Reserved

Reserved

Reserved

Reserved

SPINOR

FlexSPI

NAND

MMC/eMMC

SD/eSD

Reserved

Flash Auto Probe

 FLASH Auto Probe Type

 

CS select SPI only:

00 - CS#0  default

01 - CS#1

10 - CS#2

11 - CS#3

i.MX8M Mini ROM Fuse

Picture14.4 Table For Boot Configure

14.4 Giga Ethernet

Use a 0.1uF capacitor as bypass capacitor connect to TCT and RCT of the transformer but do not
connect these pins to any power supply.
The 49.9R and capacitor matching networks are not necessary to the differential network. The
designer should decide using these resistors and capacitors or not according to their design.
For LED_ACT Pin that is J2.45, parallel LED output for 10/100/1000 BASE-T activity, active blinking.
LED active low and is 3.3V tolerated.
For LED_1000 Pin that is J2.47, parallel LED output for 1000 BASE-T link, LED active low and is
3.3V tolerated.
For LED_10_100 Pin that is J2.43, parallel LED output for 10/100 BASE-T link. LED active low and
is 3.3V tolerated.

Picture14.5 LED Status

Summary of Contents for SOM-IMX8M-MINI

Page 1: ...1 SOM IMX8M MINI...

Page 2: ...Pinout Description Table 13 9 Power Supply And System Resets 20 9 1 Power Source 20 9 2 Power Control and Monitoring 20 9 3 System power 20 9 4 Power Consumption Typical Values 20 10 System Resets 21...

Page 3: ...2GB DDR4 up to 64GB eMMC and a WiFi Bluetooth module and with MIPI DSI display driver MIPI CSI camera receiver flexible audio interfaces and comprehensive communication features The SOM IMX8M MINI Mo...

Page 4: ...Picture2 2 Bottom side of SOM IMX8M MINI o Up to Quad core ARM Cortex A53 o 64 bit Armv8 A architecture o Target frequency up to 1 8GHz o 2D 3D GC520L o Media Processing Engine MPE with NEON technolog...

Page 5: ...bit Quad SPI Flash on board 3 60Pin 0 5mm pitch BTB connectors Up to 75xGPIO including SPI I2C PWM UART SAI and SDIO 2 2 DEV IMX8M MINI Picture2 3 DEV IMX8M MINI 12V Power IN x 1 USB 2 0 Host x 2 USB...

Page 6: ...For 4G module and PCIE module CAN Bus x 1 RS485 Bus x 1 Input Terminal x 2 PIN With Isolation Output Terminal x 2 PIN With Isolation Headphone Output MIC In x 1 SPDIF Out x 1 1x Gigabit Ethernet on bo...

Page 7: ...Mechanical Dimension Size 50 x 40 x 7 3 mm PCB Parameter 8 layer design lead free soldering process Weight 12g Picture4 1 Mechanical Dimension of Top side Picture4 2 Mechanical Dimension of Bottom si...

Page 8: ...ymmetric Cortex A53 processors including 32 KB L1 Instruction Cache 32 KB L1 Data Cache Media Processing Engine MPE Floating Point Unit FPU Support of 64 bit Armv8 A architecture 512 KB unified L2 cac...

Page 9: ...3 0 standard Runs at 4 bits Supports system boot from SD card Network Wireless Ethernet On board 10 100 1000 Mbps Ethernet PHY Wi Fi AzureWave AW CM256SM module Wi Fi 1x1 802 11a b g n ac 2 4 5GHz SDI...

Page 10: ...10 6 2 Functional Block Diagrams The following figure is a functional block diagram of the SOM IMX8M MINI Picture6 1 Functional Block Diagrams Picture6 2 i MX 8M Mini system block diagram...

Page 11: ...cification of the connector is Picture7 1 Connector Specifications For SOM The recommended BTB connector can be mounted on baseboard is MB250 G60P B1R supplied by MTCONN an equal parameters BTB connec...

Page 12: ...12 7 2 WiFi BT Antenna Connector The antenna connector mounted on SOM is Ultra Small Surface Mount Coaxial Connector the detail of the connector is as following Picture7 3 Specifications For UFL...

Page 13: ...13 8 Pinout Description Table Picture8 1 Assemble BTB on bottom side of SOM IMX8M MINI...

Page 14: ...N USB1_DP BOOT_MODE0 USB2_DN BOOT_MODE1 USB2_DP 5V_IN CSI_DN0 DSI_DN2 CSI_DP0 DSI_DP1 DSI_DN1 DSI_DP2 CSI_DN3 CSI_CKP CSI_CKN PCIE_TX_P PCIE_TX_N CSI_DP3 Picture8 2 Pin out of J1 Table8 1 Pin Definiti...

Page 15: ...P PCIe Input B19 40 GND 41 GND 42 PCIE_TX_N PCIe Output A20 43 PCIE_CLK_N PCIe Input A21 44 PCIE_TX_P PCIe Output B20 45 PCIE_CLK_P PCIe Input B21 46 GND 47 GND 48 USB1_DN USB In Out A22 49 UART4_TXD...

Page 16: ...AC18 9 SAI1_RXC 3 3V In Out AF16 10 GND 11 SAI1_RXD2 3 3V In Out AG17 Boot CFG 2 12 SAI1_MCLK 3 3V In Out AB18 13 SAI1_RXD3 3 3V In Out AF17 Boot CFG 3 14 GND 15 SAI1_RXD4 3 3V In Out AG18 Boot CFG 4...

Page 17: ...NVCC_SD2 In Out AA26 38 GND 39 SD2_WP NVCC_SD2 In Out AA27 40 SD2_CLK NVCC_SD2 In Out W23 41 GND 42 GND 43 LED_10_100 ETH _2V5 In Out 24 AR8035 44 SD2_DATA3 NVCC_SD2 In Out V23 45 LED_ACT ETH _2V5 In...

Page 18: ...0 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 Picture8 4 Pin out of J3 Table8 3 Pin Definition of J3 J3 Number Signal Power...

Page 19: ...SAI3_MCLK 3 3V In Out AD6 41 SPDIF_RX 3 3V In Out AG9 42 GND 43 SPDIF_TX 3 3V In Out AF9 44 GPIO1_IO13 3 3V In Out AD9 45 GPIO1_IO08 3 3V In Out AG10 46 GPIO1_IO12 3 3V In Out AB10 47 GPIO1_IO09 3 3V...

Page 20: ...board ICs Tolerance for power supply is 5V 0 3V Caution 1 Do not connect the ETH _2V5 VDD_3V3 NVCC_SD2 power output pins to any high current devices or you might brownout the system These power lines...

Page 21: ...urn to the range 90 110 of their nominal values 10 3 Software Reset This type of reset is activated by software running on the SOM through performing the i MX 8M MINI software reset sequence 10 4 Exte...

Page 22: ...MIPI DSI PCIE USB and Giga Ethernet Those signals are high speed signals that require the total etched trace lengths to be equal to each other Due to space constraints on the SOM the trace length of...

Page 23: ...497 04 PCIE_TX_N 623 25 634 84 PCIE_TX_P 649 18 674 21 USB1 USB1_DN 647 78 654 52 USB1_DP 652 37 693 9 USB2 USB2_DN 676 18 693 89 USB2_DP 680 79 733 26 Ethernet ETH_TRN0 246 14 172 62 ETH_TRP0 250 02...

Page 24: ...onfiguration should source from SOM board to avoid any unpredictable failure The power output pins are J3 21 and J3 23 The following figure shows to boot up from eMMC on SOM board Picture14 3 Boot up...

Page 25: ...R50 011 SDR104 101 Reserved for DDR50 Others Reserved Reserved Toggle Mode 33MHz Preamble Delay Read Latency 000 16 GPMICLK cycles 001 1 GPMICLK cycles 010 2 GPMICLK cycles 011 3 GPMICLK cycles 100 4...

Page 26: ...wer the memory card and NVCC_SD2 DO NOT use to power other devices The voltage level of NVCC_SD2 can be changed through software to support the high speed mode Note that maximum current output is 150m...

Page 27: ...ring reset input without PU PD After reset input with PD 14 7 PCIe Clock In order to boot up the system smoothly a PCIe differential clock input is necessary For example a 100MHz differential clock in...

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