Emerson ATCA-8310, Manual

Page: 357 / 460

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72D)
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8.2.3.8 Hardware Protection
In the project some of the used FPGA are identical. During debugging, it is possible that an
FPGA is configured unintended with a wrong bitstream. Because each pinning of the FPGA
devices is different, signal contention may occur and may damage devices.
Identical FPGA devices have ID Pins, which have some pin locations on the identical FPGA
devices. The ID is hardcoded on the board.
After the FPGA is configured, the hardware protection logic checks if the ID matches the loaded
image. In the case of a mismatch, all output ports will be tristate. The board will be not working,
but is protected against signal contentions.
8.2.3.9 Glue Logic FPGA Configuration Supervision
The Soft Error Detect (SED) hardware in the LatticeECP2/M devices consists of an access point
to FPGA configuration memory, a controller circuit, and a 32-bit register to store the CRC for a
given bitstream. The SED hardware reads serial data from the FPGA's configuration memory
and calculates a CRC. The data that is read, and the CRC that is calculated, does not include EBR
memory or PFUs used as RAM. The calculated CRC is then compared with the expected CRC
that was stored in the 32-bit register. If the CRC values match it indicates that there has been
no configuration memory corruption, but if the values differ an error signal (CONF_CRC_ERR)
is generated.
The Hardware Protection Logic needs to be implemented in all FPGA devices, where
identical FPGA devices are used. For example: Glue Logic FPGA and DSP FPGA.