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7

This  will clear the following SC26C92 registers: SRA, SRB, IMR, ISR, OPR, and OPCR.  It will also put OP0-OPT into the high state, stop
the counter/timer, and make channel A and B inactive with the TxDA and TxDB outputs in the high state.

After reset OP2-4 default as general purpose outputs.  If after reset they have been programmed for another function they may be
programmed to outputs again by programming register OPCR (see data sheets).   When these ports are configured as outputs they output
the complement of the data in OPR (an internal register of the SC26C92) which is controlled by the OUTSET and OUTRES ports.  
For example, to make OP2 high we must make bit 2 of OPR low (since the complement of OPR is output).   A 1 in any of the bits that are
written to the OUTRES port will result in the corresponding bit in OPR being brought low (reset), allowing you to selectively reset any or all
of the bits without affecting the others.  The following code does this.

CLR

P5.1

; enable MMIO

MOV

DPH,#OUTRES

; select OUTRES port

MOV

A,#00000100B

; bit 2 of A is set

MOVX

@DPTR,A

; write A to OUTRES, resetting bit 2 of OPR only

...subsequently writing the same value to OUTSET port will make OP2 high:

MOV

DPH,#OUTSET

; select OUTSET port

MOVX

@DPTR,A

; write A to OUTSET, setting bit 2 of OPR only

As shown above, OUTSET works the same as OUTRES except it selectively sets bits in OPR.

The inputs IP0, IP1, IP2, IP3 and IP6 may be programmed to be general purpose inputs; they are unlatched and may be examined by
simply reading the UARTIN port and examining bits 0,1,2,3 and 6.  The inputs IP0-IP3 have a unique feature in that they can also detect a
change in state.  This is defined as a high-to-low, or low-to-high input transition that lasts longer than 50 uS.  When the IPCR port is read,
bits 0-3 will read the same as the corresponding bits in the UARTIN port, and bits 4-7 if set to 1 will indicate a change of state for IP0-IP3
respectively.  After the port is read, bits 4-7 are automatically reset.  

For more details on SC26C92 input and output, see the SC26C92 data sheets.

ANALOG INPUTS

The 8 channels of 8 bit A/D have a range of 0-5V.  The upper end of this range is fine
tuned when the unit is built and may be adjusted using VR1 if it later gets out of spec.  The
range defaults to 0-5V but the upper and lower range may be programmed to other values
(within a 0-5V range) by writing to the 80535 special function register DAPR  (For more
information, see assembly language drivers and  section 3.5 of the SAB 80515/80535
Single-Chip Microcontroller User's Manual included in the appendices)

You may select 1 of 8 channels to read the data from and when the conversion is finished,
read the data from register ADDAT.  Below is a simple A/D conversion subroutine: 

           Analog Input HDR4
                1

analog channel 0 

o o

 ANL GND  

analog channel 1 

o o

 ANL GND

analog channel 2 

o o

 ANL GND

analog channel 3 

o o

 ANL GND

analog channel 4 

o o

 ANL GND

analog channel 5 

o o

 ANL GND

analog channel 6 

o o

 ANL GND

analog channel 7 

o o

 ANL GND

          ground 

o o

 ground

            +VIN 

o o

 VCC 

               19

20

; ADCIN
; Return ACC with the 8 bit A/D conversion from the channel selected by ACC
;
ADCIN: 
         ANL      A,#111B           ; ONLY 8 CHANNELS
         ANL      ADCON,#11000000B  ; MODE FOR A/D CONVERSION: SINGLE
         ORL      ADCON,A           ; "OR" IN THE CHANNEL
         MOV      DAPR,#0           ; START CONV W/NO REF VOLTAGE
         JB       BSY,$             ; LOOP TILL CONVERTED
         MOV      ACC,ADDAT         ; ACC = CONVERSION 
         RET

Summary of Contents for MicroPac 535

Page 1: ...AND CONTROL CARBONDALE IL 62901 618 529 4525 MicroPac 535 HARDWARE REFERENCE MANUAL for Revision 2 boards MANUAL Revision 2 0 Copyright 1993 1997 EMAC Inc UNAUTHORIZED COPYING DISTRIBUTION OR MODIFIC...

Page 2: ...use of this manual or the equipment that it documents EMAC reserves the right to make changes at any time FCC COMPLIANCE EMAC s MicroPac series of computers and accessories are classified as sub assem...

Page 3: ...G INPUTS 7 SERIAL PORTS 8 COM0 8 COM0 HANDSHAKE LINES 9 COM1 AND COM2 9 COM1 COM2 HANDSHAKE LINES 11 TIMER COUNTERS 13 TIMER 0 AND TIMER 1 13 TIMER 2 13 C T 13 SIGNAL OUTPUTS 14 WATCHDOG TIMER 14 INTE...

Page 4: ...4 CHANNELS OF D A This Digital to Analog convertor provides 4 channels of 8 bit resolution in the range of 0 to 5V 24 BITS OF DIGITAL I O There are 3 input lines 3 output lines and 18 lines programmab...

Page 5: ...ex to select the same RAM addresses To enable this the jumpers should be set as shown below 1 2 3 4 5 6 JP1 o o o o o o MEMORY MAP 0000 8000 FFFF PROGRAM MEMORY 32K EPROM PROGRAM DATA MEMORY 32K RAM A...

Page 6: ...routines could handle bank switching to allow calling of routines in another bank reading data memory and reading writing external RAM When 128K devices are used in both U11 and U12 the upper 64K of R...

Page 7: ...d into the Flash starting at 1 0000 instead of 0 0000 In circuit writing to a 128K Flash with a 128K RAM installed requires the same as the previous with the following exceptions The subroutine which...

Page 8: ...nnels A B C and D correspond to DPH values 10H to 13H respectively 00H 0FH 0000H 0FFFH SC26C92 COM1 COM2 timer counter and digital I O ports Below is a detailed list of the SC26C92 s ports wr indicate...

Page 9: ...CON 3 GETKEY LOOP TILL TRANSITION SENSED MOV DPH KEYPORT POINT TO KEYPAD PORT MOVX A DPTR GET THE KEY ANL A 00011111B MASK OFF UNUSED BITS CLR TCON 3 CLEAR INT1 EDGE FLAG RET DIGITAL TO ANALOG CONVERT...

Page 10: ...ndices PX18 PX23 and IP0 IP1 The remaining lines PX18 PX23 are supplied by the SC26C92 with OP2 OP3 and OP4 being output only and IP0 IP1 IP2 IP3 and IP6 being input only The inputs IP0 and IP1 are on...

Page 11: ...IP3 have a unique feature in that they can also detect a change in state This is defined as a high to low or low to high input transition that lasts longer than 50 uS When the IPCR port is read bits...

Page 12: ...or received a start bit of 0 8 data a programmable 9th bit and a stop bit of 1 When transmitting the 9th bit comes from TB8 in SCON This could be used to hold the parity of the data When receiving th...

Page 13: ...ts are in the SC26C92 with COM1 and COM2 corresponding to channel A and channel B respectively The ports are very versatile as seen in the following list of features Quadruple buffered receiver data r...

Page 14: ...2 level one bit time afterward In the RS 422 configuration OP0 and OP1 are used to enable the transmitters for COM1 and COM2 respectively Use the OUTRES command to enable and OUTSET to disable Because...

Page 15: ...RET Serial port B input SERINB MOV P2 SRB SERINB1 MOVX A R1 JNB ACC 0 SERINB1 LOOP TILL RXrdy MOV P2 RHRB READ DATA PORT MOVX A R1 RET Serial port A output SEROUTA MOV P2 SRA PUSH ACC SAVE CHAR SOUTA...

Page 16: ...GND o o PX22 OP4 GND o o PX23 IP6 2 1 Capture mode 0 can be used to decode 4 PWM signals with 16 bits of resolution again using the CC0 CC1 CC2 and CC3 lines as capture input signals remember P1 0 1...

Page 17: ...6C92 has a single interrupt output with eight maskable interrupt sources As these devices are configured on the MicroPac 535 this works out to 9 external interrupt sources 10 available when timer 2 re...

Page 18: ...ge of state occurs on any of the IP0 IP3 inputs See Digital I O section for description of change of state and see the SC26C92 data sheets for detailed information interrupts and associated registers...

Page 19: ...APPENDIX A SAB 80515 80535 Single Chip Microcontroller User s Manual Reprinted with permission from Siemens Components Inc Copyright Siemens Components Inc...

Page 20: ...APPENDIX B SC26C92 Programming and Data Reference Sheets Reprinted with permission from Philips Semiconductors Copyright Philips Semiconductors...

Page 21: ...APPENDIX C SAB 8051 Family Instruction Set Reprinted with permission from Siemens Components Inc Copyright Siemens Components Inc...

Page 22: ...APPENDIX D MicroPac 535 Schematics...

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Page 27: ...EPROM and is now used as a selector which exchanges the locations of the memory devices this jumper position also connects DO to DI which requires different SEEPROM drivers On reset P5 4 is high which...

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