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Elan Elan EM78P259N/260N, Product Specification, Page: 24 / 89

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Elan Elan EM78P259N/260N Product Specification Download Page 24

EM78P259N/260N

 

8-Bit Microprocessor with OTP ROM

 

 

18 

•

 

Product Specification (V1.2) 05.18.2007

 

 

(This specification is subject to change without further notice) 

 

0

 = increment if the transition from low to high takes place on the  

     TCCC pin 

 

1

 = increment if the transition from high to low takes place on the  

      TCCC pin 

6.2.6  IOCA0 (IR and TCCC Scale Control Register) 

Bit 7 

Bit 6 

Bit 5 

Bit 4 

Bit 3 

Bit 2 

Bit 1 

Bit 0 

TCCCSE TCCCS2 TCCCS1 TCCCS0 

IRE 

HF 

LGP 

IROUTE 

Bit 7 (TCCCSE): 

Scale enable bit for TCCC 

 

An 8-bit counter is provided as scaler for TCCC and IR-Mode.  When 

in IR-Mode, TCCC counter scale uses the low time segments of the 
pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in 
Section 6.8.2, 

Function Description

).   

 

0

 = scale disable bit, TCCC rate is 1

:

1 

 

1

 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4 

Summary of Contents for Elan EM78P259N/260N

Page 1: ...EM78P259N 260N 8 Bit Microprocessor with OTP ROM Product Specification DOC VERSION 1 2 ELAN MICROELECTRONICS CORP May 2007...

Page 2: ...is furnished under a license or nondisclosure agreement and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in life s...

Page 3: ...ibration Register 12 6 1 11 RB ADDATA Converted Value of ADC 12 6 1 12 RC ADDATA1H Converted Value of ADC 13 6 1 13 RD ADDATA1L Converted Value of ADC 13 6 1 14 RE Interrupt Status 2 Wake up Control R...

Page 4: ...4 6 7 1 ADC Control Register AISR R8 ADCON R9 ADOC RA 44 6 7 1 1 R8 AISR ADC Input Select Register 44 6 7 1 2 R9 ADCON AD Control Register 45 6 7 1 3 RA ADOC AD Offset Calibration Register 46 6 7 2 AD...

Page 5: ...67 6 13 3 Customer ID Register Word 2 68 6 14 Instruction Set 68 7 Absolute Maximum Ratings 70 8 DC Electrical Characteristics 71 8 1 AD Converter Characteristics 73 8 2 Comparator OP Characteristics...

Page 6: ...section Fig 4 1 EM78P259N 260N Functional Block Diagram Fig 6 2 TCC and WDT Block Diagram and Fig 6 11 IR PWM System Block Diagram 2 Modified Section 6 7 Analog to Digital Converter ADC 3 Modified Se...

Page 7: ...0 C 70 C Commercial Operating temperature 40 C 85 C Industrial Operating frequency range Crystal mode DC 20MHz 2clks 5V DC 100ns inst cycle 5V DC 8MHz 2clks 3V DC 250ns inst cycle 3V ERC mode DC 16MH...

Page 8: ...13 12 11 P52 ADC2 P53 ADC3 P54 TCC VREF RESET Vss P60 INT P61 TCCA P62 TCCB P63 TCCC P55 OSCI P70 OSCO VDD P67 IR OUT P65 CIN EM78P260N P64 CO P66 CIN P50 ADC0 P51 ADC1 P56 P57 Fig 3 2 EM78P260NP M K...

Page 9: ...rystal input terminal or external clock input pin RC type RC oscillator input pin OSCO 15 I O Crystal type Crystal input terminal or external clock input pin RC type clock output with a duration of on...

Page 10: ...t terminal or external clock input pin RC type RC oscillator input pin OSCO 16 I O Crystal type Crystal input terminal or external clock input pin RC type clock output with a duration of one instructi...

Page 11: ...of the IOCC1 register is cleared when a value is written to the TCC register when a value is written to the TCC prescaler bits Bits 3 2 1 0 of the CONT register during power on reset RESET or WDT tim...

Page 12: ...nd the ninth and above bits of the PC will increase progressively MOV R2 A allows loading of an address from the A register to the lower 8 bits of the PC and the ninth and tenth bits A8 A9 of the PC w...

Page 13: ...egister 1 10 1F General Registers 20 3F Bank 0 Bank 1 IOCX1 PAGE registers IOC80 Comparator and TCCA Control Register IOC90 TCCB and TCCC Control Register IOCA0 IR and TCCC Scale Control Register IOCC...

Page 14: ...RETL RETI instruction does not change the PS0 bit That is the return address will always be back to the page from where the subroutine was called regardless of the current PS0 bit setting PS0 Program...

Page 15: ...d as 0 With Simulator C3 C0 RCM1 RCM0 are IRC calibration bits in IRC oscillator mode Under IRC oscillator mode of ICE259N simulator these are the IRC mode selection bits and IRC calibration bits Bit...

Page 16: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE3 ADE2 ADE1 ADE0 Bit 7 Bit 4 Not used Bit 3 ADE3 AD converter enable bit of P53 pin 0 Disable ADC3 P53 functions as I O pin 1 Enable ADC3 to function as analog...

Page 17: ...e If P54 TCC VREF functions as VREF analog input pin then CONT Bit 5 TS must be 0 The P54 TCC VREF pin priority is as follows Bit 6 Bit 5 CKR1 CKR0 Prescaler of oscillator clock rate of ADC 00 1 16 de...

Page 18: ...I Calibration enable bit for ADC offset 0 Calibration disable 1 Calibration enable Bit 6 SIGN Polarity bit of offset voltage 0 Negative voltage 1 Positive voltage Bit 5 Bit 3 VOF 2 VOF 0 Offset voltag...

Page 19: ...is cleared and the ADIF see Section 6 1 14 RE Interrupt Status 2 Wake up Control Register is set RD is read only 6 1 14 RE Interrupt Status 2 Wake up Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi...

Page 20: ...errupt occurs RF can be cleared by instruction but cannot be set IOCF0 is the relative interrupt mask register Reading RF will result to logic AND of RF and IOCF0 Bit 7 LPWTIF Internal low pulse width...

Page 21: ...writable Bit 6 is read only Bit 7 INTE INT signal edge 0 interrupt occurs at the rising edge on the INT pin 1 interrupt occurs at the falling edge on the INT pin Bit 6 INT Interrupt enable flag 0 mas...

Page 22: ...its Only the lower 1 bit of IOC70 can be defined the other bits are not available IOC50 IOC60 and IOC70 registers are all readable and writable 6 2 4 IOC80 Comparator and TCCA Control Register Bit 7 B...

Page 23: ...to enable the most significant byte of counter 0 Disable the most significant byte of TCCBH default value TCCB is an 8 bit counter 1 Enable the most significant byte of TCCBH TCCB is a 16 bit counter...

Page 24: ...in 6 2 6 IOCA0 IR and TCCC Scale Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCCCSE TCCCS2 TCCCS1 TCCCS0 IRE HF LGP IROUTE Bit 7 TCCCSE Scale enable bit for TCCC An 8 bit counter...

Page 25: ...uses the low time segments of the pulse generated by Fcarrier frequency modulation see Fig 6 11 in Section 6 8 2 Function Description When HP 0 the TCCC is an Up Counter Bit 2 HF High Frequency bit 0...

Page 26: ...bit used to enable the pull down function of the P52 pin Bit 1 PD51 Control bit used to enable the pull down function of the P51 pin Bit 0 PD50 Control bit used to enable the pull down function of th...

Page 27: ...le the pull high function of the P53 pin Bit 2 PH52 Control bit used to enable the pull high function of the P52 pin Bit 1 PH51 Control bit used to enable the pull high function of the P51 pin Bit 0 P...

Page 28: ...0 0 1 2 0 0 1 1 4 0 1 0 1 8 0 1 1 1 16 1 0 0 1 32 1 0 1 1 64 1 1 0 1 128 1 1 1 1 256 6 2 11 IOCF0 Interrupt Mask Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LPWTIE HPWTIE TCCCIE TCCBIE TC...

Page 29: ...it 0 Disable EXIF interrupt 1 Enable EXIF interrupt Bit 1 ICIE ICIF interrupt enable bit 0 Disable ICIF interrupt 1 Enable ICIF interrupt Bit 0 TCIE TCIF interrupt enable bit 0 Disable TCIF interrupt...

Page 30: ...6 TCCB cnt x 2 CLK 4 6 2 15 IOC81 TCCC Counter The IOC81 TCCC is an 8 bit clock counter that can be extended to 16 bit counter It can be read written and cleared on any reset condition If HF Bit 2 of...

Page 31: ...etched from Address 015H Low time 6 2 17 IOCA1 High Time Register The 8 bit High time register controls the inactive or High period of the pulse The decimal value of its contents determine the number...

Page 32: ...0 Low time Rate 0 0 0 1 2 0 0 1 1 4 0 1 0 1 8 0 1 1 1 16 1 0 0 1 32 1 0 1 1 64 1 1 0 1 128 1 1 1 1 256 6 2 19 IOCC1 TCC Prescaler Counter The TCC prescaler counter can be read and written to PST2 PST1...

Page 33: ...K Fosc 4 is dependent to the Code Option bit CLKS CLK Fosc 2 if the CLKS bit is 0 and CLK Fosc 4 if the CLKS bit is 1 If TCC signal source is from an external clock input TCC will increase by 1 at eve...

Page 34: ...nd WDT Block Diagram 6 4 I O Ports The I O registers Port 5 Port 6 and Port 7 are bi directional tri state I O ports Port 5 is pulled high and pulled down internally by software Likewise P6 has its op...

Page 35: ...X PORT Q Q _ D D Q Q _ CLK P R C L CLK P R C L Note Open drain is not shown in the figure Fig 6 3 I O Port and I O Control Register Circuit for Port 6 and Port 7 PCRD IOD PCWR PDWR PDRD Bit 6 of IOCE...

Page 36: ...further notice PCRD M U X IOD 0 1 PDRD P50 P57 PCWR D Q Q _ CLK P R C L PDWR D Q Q _ CLK P R C L P R C L CLK D Q Q _ TI n PORT Note Pull high down is not shown in the figure Fig 6 5 I O Port and I O C...

Page 37: ...I O Port 5 MOV R5 R5 2 Execute ENI or DISI 3 Enable interrupt Set IOCF0 ICIE 1 b After Port 5 pin changed interrupt 1 IF ENI Interrupt vector 006H 2 IF DISI Next instruction 6 5 Reset and Wake up 6 5...

Page 38: ...AD conversion completed if ADWE enable The first two cases 1 2 will cause the EM78P260N to reset The T and P flags of R3 can be used to determine the source of the reset wake up Cases 3 4 5 are consi...

Page 39: ...wake up time is 15 TAD ADC clock period If Port 5 Input Status Change Interrupt is used to wake up the EM78P259N 260N as in Case b above the following instructions must be executed before SLEP BC R3 7...

Page 40: ...E ICWE Bit1 1 ENI IOCF0 ICIE Bit1 1 ENI IOCF0 ICIE Bit1 1 Port 5 Input Status Change Wake up Interrupt Vector 006H Set RF ICIF 1 Oscillator TCC TCCX and IR PWM are stopped Interrupt Vector 006H Set RF...

Page 41: ...NI IOCE0 CMPIE Bit4 1 Comparator Comparator Output Status Change Wake up Interrupt Vector 00FH Set RE CMPIF 1 Oscillator TCC TCCX and IR PWM are stopped Interrupt Vector 00FH Set RE CMPIF 1 DISI IOCF0...

Page 42: ...0 0 0 0 0 0 0 1 RESET and WDT 0 0 0 0 0 0 0 1 N A IOC70 Wake up from Pin Change P P P P P P P P Bit Name X X CMPOUT COS1 COS0 TCCAEN TCCATS TCCATE Power on 0 0 0 0 0 0 0 0 RESET and WDT 0 0 0 0 0 0 0...

Page 43: ...p from Pin Change P P P P P P P P Bit Name TCCA7 TCCA6 TCCA5 TCCA4 TCCA3 TCCA2 TCCA1 TCCA0 Power on 0 0 0 0 0 0 0 0 RESET and WDT 0 0 0 0 0 0 0 0 N A IOC51 TCCA Wake up from Pin Change P P P P P P P P...

Page 44: ...TCCPC0 Power on 0 0 0 0 0 0 0 0 RESET and WDT 0 0 0 0 0 0 0 0 N A IOCC1 TCCPC Wake up from Pin Change P P P P P P P P Bit Name INTE INT TS TE PSTE PST2 PST1 PST0 Power on 1 0 1 1 0 0 0 0 RESET and WD...

Page 45: ...and WDT 1 1 1 1 1 1 1 1 0x06 R6 Wake up from Pin Change P P P P P P P P Bit Name P70 Power on 0 0 0 0 0 0 0 1 RESET and WDT 0 0 0 0 0 0 0 1 0x7 R7 Wake up from Pin Change P P P P P P P P Bit Name ADE3...

Page 46: ...Bit Name ADIF CMPIF ADWE CMPWE ICWE Power un 0 0 0 0 0 0 0 0 RESET and WDT 0 0 0 0 0 0 0 0 0xE RE ISR2 Wake up from Pin Change P P P P P P P P Bit Name LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF EXIF ICIF TC...

Page 47: ...er on 0 1 1 WDTC instruction P 1 1 WDT time out 0 0 P SLEP instruction P 1 0 Wake up on pin changed during Sleep mode 1 1 0 P Previous value before reset 6 6 Interrupt The EM78P259N 260N has six inter...

Page 48: ...he interrupt service routine to avoid recursive interrupts The flag except for the ICIF bit in the Interrupt Status Register RF is set regardless of the ENI execution Note that the result of RF will b...

Page 49: ...STACKR4 Fig 6 9 Interrupt Backup Diagram In EM78P259N 260N each individual interrupt source has its own interrupt vector as depicted in the table below Interrupt Vector Interrupt Status Priority 003H...

Page 50: ...is fed to the ADDATA ADDATA1H and ADDATA1L Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS1 and ADIS0 ADDATA1H DATA BUS ADC3 ADC2 ADC1 ADC0 Vref Power Dow...

Page 51: ...on of the AD conversion and determines which pin should be currently active Bit 7 VREFS Input source of the ADC Vref 0 The ADC Vref is connected to Vdd default value and the P54 VREF pin carries out t...

Page 52: ...nalog Input Select 00 ADIN0 P50 01 ADIN1 P51 10 ADIN2 P52 11 ADIN3 P53 These bits can only be changed when the ADIF bit and the ADRUN bit are both LOW 6 7 1 3 RA ADOC AD Offset Calibration Register Bi...

Page 53: ...ted 6 7 4 AD Conversion Time CKR1 and CKR0 select the conversion time Tct in terms of instruction cycles This allows the MCU to run at a maximum frequency without sacrificing the AD conversion accurac...

Page 54: ...rocess Follow these steps to obtain data from the ADC 1 Write to the four bits ADE3 ADE0 on the R8 AISR register to define the characteristics of R5 digital I O analog channels or voltage reference pi...

Page 55: ...rol Register IOC50 0X5 Control Register of Port 5 IOC60 0X6 Control Register of Port 6 C_INT 0XF Interrupt Control Register C ADC Control Register ADDATA 0xB The contents are the results of ADC AISR 0...

Page 56: ...define P50 as an input pin and the others IOW PORT5 are dependent on applications MOV A 0BXXXX1XXX Enable the ADWE wake up function of ADC X by application MOV RE A MOV A 0BXXXX1XXX Enable the ADIE in...

Page 57: ...me register and IOC91 low time register H W Modulator 8 HF IROUT pin IRE Fcarrier FT CLK Fosc LGP 8 Bit counter 8 to 1 MUX 8bit binary down counter Auto reload buffer TCCC IOC81 8 Bit counter 8 to 1 M...

Page 58: ...UT waveform modulates the Fcarrier waveform at low time segments of the pulse Fig 6 12a LGP 0 HF 1 IROUT Pin Output Waveform The following figure shows LGP 0 and HF 0 The IROUT waveform cannot modulat...

Page 59: ...e following figure shows LGP 0 and HF 0 The IROUT waveform cannot modulate the Fcarrier waveform at low time segments of the pulse So IROUT waveform is determined by high time width and low time width...

Page 60: ...IOC90 TCCBHE 0 TCCBEN 0 TCCBTS 0 TCCBTE 0 0 TCCCEN 0 TCCCTS 0 TCCCTE 0 0X0A IR CR IOCA0 TCCCSE 0 TCCCS2 0 TCCCS1 0 TCCCS0 0 IRE 0 HF 0 LGP 0 IROUTE 0 0x0F IMR IOCF0 LPWTIE 0 HPWTIE 0 TCCCIE 0 TCCBIE...

Page 61: ...EM78P259N 260N 8 Bit Microprocessor with OTP ROM Product Specification V1 2 05 18 2007 55 This specification is subject to change without further notice...

Page 62: ...CCS1 TCCCS0 Fig 6 13 Timer Block Diagram Each signal and block of the above TIMER block diagram is described as follows TCCX Timer A C register TCCX increases until it matches with zero and then reloa...

Page 63: ...sc x 65536 TCCBH 256 TCCB cnt x 2 CLK 4 Under TCCC Counter IOC81 IOC81 TCCC is an 8 bit clock counter It can be read written and cleared on any reset condition If HF Bit 2 of IOCA0 1 and IRE Bit 3 of...

Page 64: ...TCCCIE 0 TCCBIE 0 TCCAIE 0 EXIE 0 ICIE 0 TCIE 0 Related TCCX Status Data Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0F ISR RF LPWTF 0 HPWTF 0 TCCCIF 0 TCCBIF 0 TCCAIF 0...

Page 65: ...ither pin of the comparator Threshold detector applications may be of the same reference The comparator can operate from the same or different reference sources 6 10 2 Comparator Output The compared r...

Page 66: ...ed by reading the Bit CMPOUT IOC80 5 CMPIF RE 4 the comparator interrupt flag can only be cleared by software 6 10 5 Wake up from Sleep Mode If the CMPWE bit of the RE register is set to 1 the compara...

Page 67: ...e P70 OSCO acts as P70 0 0 0 ERC 1 External RC oscillator mode P70 OSCO acts as OSCO 0 0 1 IRC 2 Internal RC oscillator mode P70 OSCO acts as P70 0 1 0 IRC 2 Internal RC oscillator mode P70 OSCO acts...

Page 68: ...ies to the HXT mode and the LXT mode OSCI EM78P259N EM78P260N OSCO Crystal RS C2 C1 Fig 6 17 Crystal Resonator Circuit The following table provides the recommended values for C1 and C2 Since each reso...

Page 69: ...noted that the frequency of the RC oscillator is influenced by the supply voltage the values of the resistor Rext the capacitor Cext and even by the operation temperature Moreover the frequency also c...

Page 70: ...z 540kHz 5 1k 370kHz 360kHz 10k 196kHz 192kHz 300 pF 100k 20kHz 20kHz Note 1 Measured based on DIP packages 2 The values are for design reference only 3 The frequency drift is 30 6 11 4 Internal RC Os...

Page 71: ...tically the range is from 4 5ms or 18ms For most crystal or ceramic resonators the lower the operation frequency is the longer is the required set up time 6 12 2 External Power on Reset Circuit The ci...

Page 72: ...removed but the residual voltage remains The residual voltage may trip below Vdd minimum but not to zero This condition may cause a poor power on reset Fig 6 22 and Fig 6 23 show how to create a prot...

Page 73: ...ods default Refer to Section 6 15 for Instruction Set Bit 7 ENWDTB Watchdog timer enable bit 0 Enable 1 Disable default Bits 6 5 4 OSC2 OSC1 OSC0 Oscillator Mode Selection bits Oscillator Modes OSC2 O...

Page 74: ...7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCOUT NRHL NRE WDTPS CYES C3 C2 C1 C0 RCM1 RCM0 Bits 12 11 Not used reserved These bits are set to 1 all the time Bit 10 RCOUT Instruction clock output ena...

Page 75: ...Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X X X X X Bit 12 0 Customer s ID code 6 14 Instruction Set Each instruction in the instruction set is a 13 bit word divided into a...

Page 76: ...000 0001 0000 0010 ENI Enable Interrupt None 0 0000 0001 0001 0011 DISI Disable Interrupt None 0 0000 0001 0010 0012 RET Top of Stack PC None 0 0000 0001 0011 0013 RETI Top of Stack PC Enable Interrup...

Page 77: ...100b bbrr rrrr 0xxx BC R b 0 R b None 2 0 101b bbrr rrrr 0xxx BS R b 1 R b None 3 0 110b bbrr rrrr 0xxx JBC R b if R b 0 skip None 0 111b bbrr rrrr 0xxx JBS R b if R b 1 skip None 1 00kk kkkk kkkk 1k...

Page 78: ...High Threshold Voltage Schmitt trigger RESET 2 0 V VILT1 Input Low Threshold Voltage Schmitt trigger RESET 1 0 V VIHT2 Input High Threshold Voltage Schmitt trigger TCC INT 3 75 V VILT2 Input Low Thres...

Page 79: ...CLKS 0 output pin floating WDT enabled 3 0 3 5 mA Note These parameters are hypothetical have not been tested and are provided for design reference only Data in the Minimum Typical and Maximum Min Ty...

Page 80: ...5 to 5 5V Ta 25 C 0 2 4 LSB DNL Differential nonlinear error Vdd 2 5 to 5 5V Ta 25 C 0 0 5 0 9 LSB FSE1 Full scale error Vdd VAREF 5 0V VASS 0 0V 0 4 8 LSB FSE2 Full scale error VDD VREF 5 0V VSS 0 0...

Page 81: ...Supply current of Comparator 300 uA PSRR Power supply Rejection Ration for OP Vdd 5 0V VSS 0 0V 50 60 70 dB Vs Operating range 2 5 5 5 V Note These parameters are hypothetical not tested and are provi...

Page 82: ...th Ta 25 C 2000 ns Twdt Watchdog timer period Ta 25 C 11 3 16 2 21 6 ms Tset Input pin setup time 0 ns Thold Input pin hold time 15 20 25 ns Tdelay Output pin delay time Cload 20pF 45 50 55 ns Tdrc ER...

Page 83: ...ing Diagrams RESET Timing CLK 0 CLK RESET NOP Instruction 1 Executed Tdrh TCC Input Timing CLKS 0 CLK TCC Ttcc Tins AC Testing Input is driven at VDD 0 5V for logic 1 and GND 0 5V for logic 0 Timing m...

Page 84: ...DIP 20 300mil EM78P260NMS NMJ SOP 20 300mil EM78P260NKMS NKMJ SSOP 20 209mil B Package Information B 1 18 Lead Plastic Dual in line PDIP 300 mil TITLE PDIP 18L 300MIL PACKAGE OUTLINE DIMENSION Unit mm...

Page 85: ...ut further notice B 2 18 Lead Plastic Small Outline SOP 300 mil TITLE SOP 18L 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free Material Edtion A Sheet 1 of 1 b e Min Normal Max 2 350 2 650 0 102 0...

Page 86: ...nk Small Outline SSOP 209 mil TITLE SSOP 20L 209MIL OUTLINE PACKAGE PACKA OUTLINE DIMENSION Unit mm Scale Free File SSOP20 Material Edtion A Sheet 1 of 1 b e c E E1 A2 Min Normal Max 2 130 0 050 0 250...

Page 87: ...in line PDIP 300 mil TITLE PDIP 20L 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File D20 Material Edtion A Sheet 1 of 1 Min Normal Max 4 450 0 381 3 175 3 302 3 429 0 203 0 254 0 356 25 883 26...

Page 88: ...ut further notice B 5 20 Lead Plastic Small Outline SOP 300 mil TITLE SOP 20L 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File SO20 Material Edtion A Sheet 1 of 1 b e Symbal A A1 b c E H D L e...

Page 89: ...C RH 100 pressure 2 atm TD durance 96 hrs High temperature High humidity test TA 85 C RH 85 TD durance 168 500 hrs High temperature storage life TA 150 C TD durance 500 1000 hrs High temperature opera...

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