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Chapter 2 

Chapter 2 

Architecture

 

2.1 Architectural Overview 

2.1.1 Overview 

Architecture 

The EM60000 series have a high performance 8-bit RISC CPU with the 
Havard-type architecture which allows the program and data to have separate 
memories in order to improve the bandwidth of data access.  Applying a 
two-level overlapped fetch-and-execute pipeline, all instructions will only 
require a single instruction cycle (except for those that modify the program 
counter).  Note that each instruction cycle takes two system clocks, resulting in 
a high instruction throughput and fast interrupt response. 

Arithmetic Logic Unit (ALU) 

The EM60000 series contain an 8-bit ALU and accumulator (ACC).  The ALU 
is a general-purpose arithmetic unit that performs 2’s-complement arithmetic 
and logical operations.  It operates under all of the data memory in direct or 
indirect address mode that includes memory-mapped control registers.  The 
ALU also supports BCD decimal arithmetic operations. 

Data Memory 

The data memory of EM60000 series has a total of 144 bytes with direct and 
indirect address modes.  Three locations of the data memory are set aside to be 
shared by the multiplier.  All operations can be applied directly to the data 
memory.  Part of the control registers are mapped to the data memory and other 
part are mapped to the IOC register (I/O mapped control register).  The data 
memory is divided into one common and four banked blocks selected by 2 
control bits. 

Hardware Multiplier 

The 8x8 hardware multiplier of EM60000 series takes only a single instruction 
cycle.  It performs signed multiplication and generates a 16-bit signed result that 
is stored in two registers mapped in the data memory.  The multiplication 
instruction can be applied on data memory or on an immediate constant, 
providing a wide range of user applications, such as Digital Signal Processing. 

EM60000 Series User’s Manual 

Architecture 

•

 5 

Summary of Contents for EM60000 series

Page 1: ...EM60000 Series 8 Bit Micro Controller Based Sound Processor USER S MANUAL ELAN MICROELECTRONICS CORP March 2003 Doc Version 2 0 ...

Page 2: ...losure agreement and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in life support appliances devices or systems Use of ELAN Microelectronics product in such applications is not supported and is prohibited NO PART OF THIS PUBLICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED...

Page 3: ...Oscillator Frequency 4 2 Architecture 5 2 1 Architectural Overview 5 2 1 1 Overview 5 2 1 2 Functional Block Diagram 6 2 1 3 Hardware Summary 7 2 2 Arithmetic Logic Unit ALU 7 2 2 1 ALU Instruction Summary 8 2 2 1 1 Boolean Instruction 8 2 2 1 2 Arithmetic Instruction 8 2 2 1 3 Bit Manipulated Instruction 9 2 2 1 4 Data Move Instruction 9 2 2 2 ALU Related Status Flags 9 2 3 Hardware Multiplier 10...

Page 4: ... O Mapped Control Registers 22 3 3 1 IOC5 Prescaler Control Register 22 3 4 Program Counter and Stack 24 3 5 Interrupts 24 3 5 1 TCC Timer Interrupt 25 3 5 2 MTC Timer Interrupt 25 3 5 3 Speech Timer Interrupt 25 3 6 Reset 26 3 7 Sleep Mode and Wake Up 27 3 7 1 WDT Wake Up 27 3 7 2 Input Port Wake Up 27 3 8 Timer Control 27 3 8 1 TCC Timer 28 3 8 2 MTC Timer 28 3 8 3 Speech Timer 29 3 8 4 Watchdog...

Page 5: ...pe Register 42 4 3 4 IOCB IOCC Frequency Registers 42 4 4 Voice ROM Access Control 42 4 4 1 IOC6 7 8 Address Registers 43 4 4 2 IOC9 ROM Data Input Registers 43 4 5 DAC Function Control 43 4 5 1 RA MODE Registers 44 4 5 2 IOC6 Selector Registers 45 5 Instruction Set 47 5 1 Introduction 47 5 2 Instruction Summary 48 5 3 Instruction Description 50 5 3 1 ADD Addition 50 5 3 2 AND And Operation 51 5 3...

Page 6: ...o 59 5 3 23 JZA Increment R and Place in Acc Skip if result is zero 60 5 3 24 MOV Move Data 60 5 3 25 MPY Multiply 61 5 3 26 NOP No Operation 62 5 3 27 OR Inclusive OR 62 5 3 28 PAGE Set Page Bits 63 5 3 29 RET Return from Subroutine 64 5 3 30 RETI Return from Interrupt 64 5 3 31 RETL Return Immediate Data to the A Register 65 5 3 32 RETS Return from Speech Subroutine 66 5 3 33 RLC Rotate Left Thr...

Page 7: ...tructions 79 6 4 5 Example Applying the SUB DEC and DECA Instructions 79 6 5 I O Port Applications 80 6 5 1 Example Input Pin Polling and Configuring Output Port 80 6 5 2 Example Simple Keyboard Scan 16 Keys 82 6 6 Interrupt Subroutine 87 6 6 1 TCC Timer Interrupt 87 6 6 2 MTC Timer Interrupt 88 6 6 2 1 Example Timer Interrupt 88 6 6 3 Speech Timer Interrupt 90 6 6 3 1 Example Speech Interrupt 91 ...

Page 8: ...Contents viii Contents EM60000 Series User s Manual ...

Page 9: ...hree general purpose I O ports that are provided By programming applications such as section combination trigger mode output control keyboard matrix and other logic functions can be easily implemented with the micro controller Together these powerful features motivate users in achieving a wide range of innovative concepts 1 2 Features Operating voltage 2 4 5 5V 8 bit RISC CPU Two general purpose t...

Page 10: ...up WDT Timers Addressing Interface Multi tone Generator Multiplier 8 8 Control Unit 1 4 Parts List The EM60000 series IC s are equipped with 8K 13 bit program ROM and 144 bytes RAM Part Number Voice ROM Input Pin I O Pin Output Pin DAC Speech Channels Melody Channels EM60001 32K 8 bits 8 Port 1 16 Port 2 3 None 2 2 4 EM60301 256K 8 bits 8 Port 1 24 Port 2 3 4 None 2 2 4 EM60600 2048K 8 bits 8 Port...

Page 11: ...60001 EM60301 VO1 O Current output of DAC 1 VO2 O Current output of DAC 2 VDD Positive power supply VSS Negative power supply TEST I For testing use only normally floating RESET I Reset pin active low internal pull high 1 6 Specifications 1 6 1 Absolute Maximum Ratings Parameter Specification Supply Voltage VDD VSS 0 3V to 6 0V Input Voltage VSS 0 3V to VDD 0 3V Operating Temperature 0 C to 50 C S...

Page 12: ... VDD 3V VOL 0 4V Sink Current of Port 2 3 4 5 IOL 12 mA VDD 3V VOL 1 5V VIH 1 8 V VDD 4 5V VIL 0 8 V VDD 4 5V VIH 1 4 V VDD 3V Input Voltage of All Input Ports Without Internal Pull low VIL 0 6 V VDD 3V II 8 12 µA VDD 4 5V Input Current With Internal Pull low II 3 5 µA VDD 3V IVO 2 3 4 mA VDD 4 5V VO 0 7V D A Output Current maximum volume IVO 2 3 4 mA VDD 3V VO 0 7V FOSC 4 8 MHz VDD 4 5V Operating...

Page 13: ...irect address mode that includes memory mapped control registers The ALU also supports BCD decimal arithmetic operations Data Memory The data memory of EM60000 series has a total of 144 bytes with direct and indirect address modes Three locations of the data memory are set aside to be shared by the multiplier All operations can be applied directly to the data memory Part of the control registers a...

Page 14: ... prescaler for controlling the melody playback instrument The other two timers are dedicated for speech voice playback By taking advantage of the full set of timer functions sophisticated multi channel instrument applications can be easily implemented 2 1 2 Functional Block Diagram ST1 ST1 MTC TCC I O pins I O Ports I O Port Control 8 13 Program ROM Address Program ROM Data IR Decode IR Stack 8 Le...

Page 15: ...call and interrupt IR Instruction register used for instruction fetch IR Decode Instruction decoder to generate control signals Address Generator Address generator for data RAM and control registers System Control Registers System control registers are useful for controlling processor melody I O functions They are memory or I O mapped Tone Generator 4 channel tone generator for melody instrument s...

Page 16: ...traction A R constant INC Increase memory content by 1 R INCA Increase memory content by 1 and load the result into ACC R DEC Decrease memory content by 1 R DECA Decrease memory content by 1 and load the result into ACC R CLR Set memory content to zero R RRC Rotate memory right 1 bit with carry bit R RRCA Rotate memory content right 1 bit with carry bit and load the result into ACC R RLC Rotate me...

Page 17: ...isters such as I O ports or control registers Example The logical AND instructions AND A 0xF0 ACC ACC 0xF0 0xF0 is constant AND A 0x10 ACC ACC content of R10 R10 is data memory AND 0x10 A R10 R10 ACC For the detailed descriptions of the instructions refer to Chapter 5 Instruction Set 2 2 2 ALU Related Status Flags The ALU related status flags are listed as the following Symbol Description C Carry ...

Page 18: ... byte Example 1 Integer multiplication 10 10 100 0x64 MOV A 10 MOV 0x10 A let R10 MULT 10 MPY 10 10 10 100 0x0064 operand is immediate value Example 2 Integer multiplication 10 10 100 0x64 MOV A 10 MOV 0x10 A let R10 MULT 10 MOV A 10 MOV 0x14 A let R14 10 MPY 0x14 10 10 100 0x0064 operand is register address Example 3 Fractional multiplication 64 0 75 48 0x40 0x60 0x1800 0x1800 left shift one bit ...

Page 19: ...s and Data Memory Address Symbol Description 0x00 R0 Indirect address register 0x01 R1 TCC 8 bit general purpose timer register 0x02 R2 PC Lower 8 bit of program counter 0x03 R3 SF Status flag register 0x04 R4 RSR RAM select register for selecting memory bank and indirect address register 0x05 R5 INTC Interrupt control register for interrupt enable function and flag 0x06 R6 MTC 8 bit general purpo...

Page 20: ...6 MTC IOC6 R7 Not used IOC7 R8 R8 IOC8 R9 R9 IOC9 RA Mode IOCA RB Port 1 IOCB RC Port 2 IOCC RD Port 3 IOCD Port 2 I O RE Port 4 IOCE Port 3 I O RF Port 5 IOCF Port 4 I O R10 MULT R11 PRODL R12 PRODH R13 R13 1F Common Data Memory R1F 00 01 10 11 R20 Bank 0 Bank 1 Bank 2 Bank 7 32x8 32x8 32x8 32x8 Data Data Data Data R3F Memory Memory Memory Memory NOTE 1 R0 and R1 indicate address is 0x00 and 0x01...

Page 21: ...t bits PS2 PS0 in the Status Flag register Hence the jump call instruction will go to the location within the page specified by PS2 PS0 Example Current page jump and cross page jump ORG 0x0000 the following code resides in page 0 JMP Label1 Label1 is located in page 0 PAGE 1 Label2 is located in page 1 JUMP Label2 Label1 MOV A 0 JMP STOP STOP is located in page 0 STOP NOP SLEP ORG 0x0400 the follo...

Page 22: ...de of data memory access MOV A 0x05 move content of R5 to ACC MOV 0x10 A move content of ACC to R10 BS 0x12 0 set bit 0 of R12 to 1 INC 0x15 increase R15 by 1 JBS 0x03 3 if bit 3 of R3 is 1 skip JZ 0x11 R11 R11 1 if R11 0 skip In Indirect Address mode the data memory accessed by the instruction is not fixed The data location to be accessed can be modified by the program during run time This featur...

Page 23: ...nerally you need to first write the address of the desired data and then read the data through a special I O mapped control register The reading operation is controlled by software Three address pointers are provided i e two for speech timer interrupt subroutine and one for general purpose voice ROM data access Alternatively when playing instrument melodies the instrument waveform is initially sto...

Page 24: ...Chapter 2 16 Architecture EM60000 Series User s Manual ...

Page 25: ...O port and wake up functions The System Control Registers are located in the unbanked area of data memory Address Symbol Description 0x03 R3 SF Status flag register 0x04 R4 RSR RAM select register for selecting memory bank and indirect address mode 0x05 R5 INTC Interrupt control register for interrupt enable disable function and interrupt flags 0x08 R8 I O ports pull low wake up and watchdog timer...

Page 26: ...to 1 with the SLEP and WDTC command or during power on reset Reset to 0 with WDT time out Bit 5 PS0 7 PS2 Page select bit PS0 PS2 are loaded into the 11th to 13th bits of the program counter selecting one of the available program memory pages The value is set with the PAGE instruction 3 2 2 R4 RAM Select Register Bits 5 0 of RAM Select Register are used for indirect address ranging from 0x00 0x3F ...

Page 27: ...hout MTC timer interrupt request MIF 1 With MTC timer interrupt request Bit 2 TCIE TCC interrupt enable bit TCIE 0 Disable TCC timer interrupt TCIE 1 Enable TCC timer interrupt Bit 3 MIE MTC melody timer interrupt enable bit MIE 0 Disable MTC timer interrupt MIE 1 Enable MTC timer interrupt Bit 7 ENI Global interrupt enable bit includes speech timer interrupts ENI 0 Disable all the interrupts even...

Page 28: ...disabled WAKEL 1 Low nibble of Port 2 has wakeup function Bit 2 WAKEH Port 2 wake up enable bit for high nibble Pin 4 7 WAKEH 0 Wakeup function of Port 2 high nibble is disabled WAKEH 1 High nibble of Port 2 has wake up function Bit 4 PL2L Port 2 pull low enable bit for low nibble Pin 0 3 PL2L 0 Pull low function of Port 2 low nibble is disabled PL2L 1 Low nibble of Port 2 has internal pull low fu...

Page 29: ... for these special functions See Special Function Control in Section 4 of this chapter for further details The control register banks function and location are summarized in the following table Register Bank Functions Control Register Locations Bank 1 Speech Channel 1 RA IOC6 IOCC Bank 2 Speech Channel 2 RA IOC6 IOCC Bank 3 Melody Channel 1 RA IOC6 IOCC Bank 4 Melody Channel 2 RA IOC6 IOCC Bank 5 ...

Page 30: ...e IOR instruction is used to read the I O Mapped Control Register and store its content in the ACC The IOW instruction is used to write the content of ACC to the I O Mapped Control Register Example Accessing I O mapped control registers IOR 0x5 read content of IOC5 then store in ACC IOR 0xF read content of IOCF then store in ACC MOV A 0 IOW 0xD write 0 to IOCD MOV A 0x10 IOW 0xE write content of R...

Page 31: ...base frequency is Fosc 2 and the initial value is 1 1 1 PSR2 PSR1 PSR0 TCC Rate 0 0 0 1 2 0 0 1 1 4 0 1 0 1 8 0 1 1 1 16 1 0 0 1 32 1 0 1 1 64 1 1 0 1 128 1 1 1 1 256 Bit 5 Bit 7 MSR0 MSR2 MCC prescaler bit The base frequency is Fosc 2 and the initial value is 1 1 1 MSR2 MSR1 MSR0 MTC Rate 0 0 0 1 2 0 0 1 1 4 0 1 0 1 8 0 1 1 1 16 1 0 0 1 32 1 0 1 1 64 1 1 0 1 128 1 1 1 1 256 EM60000 Series User s ...

Page 32: ...es only 1 instruction cycle 5 Bit Set Clear Operation Same as write operation Example Modify the program counter MOV A 0x40 MOV 0x2 A lower 8 bits of PC will be 0x40 MOV A 0x1 ADD 0x2 A PC PC 1 3 5 Interrupts Two types of Interrupts are available for the processor These are the Timer Interrupt TCC MTC and the Speech Timer Interrupt Speech Timer 1 Speech Timer 2 Interrupts These interrupts come fro...

Page 33: ... The program must clear the interrupt flag before leaving the interrupt subroutine to avoid recursive interrupts from occurring 3 5 3 Speech Timer Interrupt The Speech Timer Interrupts are used for software speech synthesis You should set the timers to its correct values which correspond to the speech sampling rate This interrupt is sourced from the Speech Timer 1 for speech Channel 1 and Speech T...

Page 34: ...rogram counter PC is set to all 0 Bits 5 7 of R3 SF are set to all 0 i e set to program Page 0 The upper 2 bits of R4 RSR are set to 0 i e select RAM Bank 0 R1 TCC and R6 MTC are all cleared The count value of the Watchdog timer and prescaler are cleared R5 INTC Bits 0 5 are cleared Bit 7 is set R8 Bits 0 2 and Bits 4 6 are all set to 0 R10 12 Multiplier All cleared IOC5 Prescaler Control Register...

Page 35: ...nues to run and the processor executes the instruction that follows after SLEP The controller will continue running the program until another reset power off or Sleep Mode condition is encountered NOTE Before going into power down mode all input ports should not be floating Otherwise there will be an extra current consumption For example Port 1 should be pulled low if no external device is connect...

Page 36: ...mer The MTC Timer is useful for controlling the tempo envelope and rhythm as well as updating the score data of the music while the instrument melody plays back It can also be treated as another general purpose timer Like the TCC timer the MTC Timer also has a prescaler The base frequency is half of the system clock Fosc 2 which is divided by the prescaler The divided clock signal is then sent to ...

Page 37: ...iggered Refer to Section 4 2 Speech Function Control of Chapter 4 for more detailed description of the Speech Timer control 3 8 4 Watchdog Timers The Watchdog timer WDT has a free running on chip RC oscillator It will keep on running even if the oscillator has been turned off i e switched into Sleep Mode During normal operation or Sleep Mode if the WDT is enabled a WDT time out forces the processo...

Page 38: ... The control registers determine the direction input or output of the bi directional ports so only Ports 2 4 are with control registers Note that the bi directional ports are configured as input ports during a reset and the initial pin status is unknown You must remember to write initial values to these ports before configuring them as output ports See the Program Initialization in Section 6 2 of ...

Page 39: ...ion is always enabled and the pull low function is controlled by R8 Hence you must set Port 1 to pull low before entering into sleep mode 3 9 2 Port 2 Port 2 is a bi directional port with internal pull low and wake up functions The pin data is latched in RC data memory address 0x0C You can read the input data or write the output data through a memory access instruction The pull low function is con...

Page 40: ...0D You can read the input data or write the output data through a memory access instruction The I O direction is controlled by IOCE I O mapped register 0xE RD Bit Field RD Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port 3 Pin P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Bit value 0 the relative pin is in LOW status Bit value 1 the relative pin is in HIGH status Each bit value reflects the stat...

Page 41: ... 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port 4 Pin P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Bit value 0 the relative pin is in LOW status Bit value 1 the relative pin is in HIGH status Each bit value reflects the status of its corresponding I O pin Because Port 4 is a bi directional port the RE register can be read or written IOCF bit field IOCF Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi...

Page 42: ... write the output data through a memory access instruction RF Bit Field RF Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port 5 Pin P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 Bit value 0 the relative pin is in LOW status Bit value 1 the relative pin is in HIGH status PDRD Pad PDWR CLR Q D PR DBUS 34 System Control EM60000Series User s Manual ...

Page 43: ...C control As described in the System Control Registers Section 3 2 of Chapter 3 the R9 Bank Select Register for Special Function Control is used for switching between these nine register banks Bit Field of R9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DASEL DASET CH2 CH1 CH0 DASEL DASET CH2 CH1 CH0 Special Function Control 00000 Speech Channel 1 00001 Speech Channel 2 00010 Voice ROM data acc...

Page 44: ... MOV A R9 read R9 into ACC AND A 0x1F mask out Bits 5 7 to obtain correct result 4 2 Speech Function Control The Speech Function Control takes care of all the speech synthesis related controls including speech interrupt setting sampling rate control and speech data address pointer When R9 0x00 or 0x01 the Control Register Bank will change to speech Channel 1 or 2 These control registers are listed...

Page 45: ...speech timer interrupt and data output to the mixer of the two D A converters Using the control bits of the MODE register the user can enable disable the speech timer interrupt and determine whether the synthesized data will be fed to the DAC mixers or not Bit field of RA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SENA SENT Bit 0 SENT SENT is used to enable disable speech timer interrupt SENT...

Page 46: ...OM data through IOC9 in two ways 1 Use an IOR instruction on IOC9 to get data in byte format from the voice ROM The address IOC6 8 will automatically increase by one Example Read voice ROM data in byte form R9 0x09 IOC6 0x6 IOC7 0x7 IOC8 0x8 IOC9 0x9 buffer 0x13 MOV A 0 set R9 0 for speech Channel 1 control MOV R9 A MOV A 0 IOW IOC6 voice ROM address 0x0000 IOW IOC7 IOW IOC8 IOR IOC9 read 1 byte v...

Page 47: ...location The remaining bits in previous ROM location will be lost Example Read 3 bits of data from the voice ROM with GET instruction R9 0x09 buffer 0x13 MOV A 0 set R9 0 for speech Channel 1 control MOV R9 A GET 3 get 3 bits from voice ROM MOV buffer A store in the buffer 4 2 4 IOCA Sampling Rate Register The IOCA stores the reload values of the speech timers The reload value controls the time in...

Page 48: ...waveform address setting instrument synthesis frequency control envelope control etc When R9 0x04 to 0x07 the control register bank will change to melody Channels 1 to 4 The control registers are listed as follows Melody Channel 1 Melody Channel 2 Melody Channel 3 Melody Channel 4 R9 0x04 R9 0x05 R9 0x06 R9 0x07 RA MODE MODE MODE MODE IOC6 ADDL ADDL ADDL ADDL IOC7 ADDM ADDM ADDM ADDM IOC8 ADDH ADD...

Page 49: ...rrent melody channel Bits 1 7 Unused NOTE 1 The reset initial value of Bit 0 is 0 2 Bits 1 7 are not used Writing data into these bits is invalid The value read from these bits is unknown 4 3 2 IOC6 7 8 Address Registers Melody Channel 17 16 15 8 7 0 IOC8 ADDH IOC7 ADDM IOC6 ADDL A total of four address pointers for instrument waveforms are available Each melody channel has its own address pointer...

Page 50: ...isters The frequency registers IOCB F1 and IOCC F2 control the tone generator frequency of the current melody channel You should provide a frequency with a correct value by referring to a frequency table F1 value should be 6 bit located in Bits 2 7 and F2 value should be 8 bit 4 4 Voice ROM Access Control The voice ROM access control can be treated as another voice ROM access window In addition to...

Page 51: ...ol The DAC function control is responsible for the mixing operation saturation control volume control and turning on off of the DAC When R9 0x08 the control register bank will change to DAC 1 control Similarly when R9 0x18 the control register bank will change to DAC 2 Only two control registers are available in DAC control i e the RA MODE register and the IOC6 Selector register RA is used to cont...

Page 52: ...xer output dynamic range Bit 4 Bit 6 VOL0 VOL2 These bits are used as DAC volume control Bits 1 7 Not used SETR1 SETR0 The reset initial value is 0 When mixing the accumulated mixer may result to a large dynamic range of up to 10 bit This may saturate DAC which has an 8 bit resolution only You can define a suitable output data range to prevent DAC from being saturated SETR1 SETR0 Output Data Sent ...

Page 53: ...Bit 0 SCH1 SCH1 0 Output of speech Channel 1 will not be sent to the mixer SCH1 1 Output of speech Channel 1 will be sent to the mixer Bit 1 SCH2 SCH2 0 Output of speech Channel 2 will not be sent to the mixer SCH2 1 Output of speech Channel 2 will be sent to the mixer Bit 2 MCH1 MCH1 0 Output of melody Channel 1 will not be sent to the mixer MCH1 1 Output of melody Channel 1 will be sent to the m...

Page 54: ...Chapter 4 46 Special Function Control EM60000Series User s Manual ...

Page 55: ...ion for bit manipulation instruction Z Zero flag C Carry flag DC Auxiliary carry flag T WDT time out flag P Power down flag n 3 bit constant Note The immediate value constant operand specified by k must be prefixed with an sign The numeric representation is listed in the following table The characters are none case sensitive Decimal 0 1 128 255 Binary 0b00000000 or 00000000B 0b00000001 or 00000001...

Page 56: ...ter R A 0 0000 0010 0nnn 002n GET n Get n bits from ROM speech Channel 1 or 2 0 0000 0011 0nnn 003n PAGE n Set program page n PS0 2 0 0000 01rr rrrr 00rr MOV R A Move Acc to register A R 0 0000 10rr rrrr 00rr MPY R Multiply R10 by R R10 R R12 R11 0 0000 11rr rrrr 00rr CLR R Clear register 0 R Z 0 0001 00rr rrrr 01rr SUB A R Substract Acc from R R A A Z C DC 0 0001 01rr rrrr 01rr SUB R A Substract ...

Page 57: ...R R 1 A If result 0 skip next instruction 0 0111 11rr rrrr 07rr JZ R R 1 R If result 0 skip next instruction 0 100b bbrr rrrr 0xxx BC R b Clear bit b of R 0 R b 0 101b bbrr rrrr 0xxx BS R b Set bit b of R 1 R b 0 110b bbrr rrrr 0xxx JBC R b if bit b of R 0 skip next instruction 0 111b bbrr rrrr 0xxx JBS R b if bit b of R 1 skip next instruction 1 00kk kkkk kkkk 1kkk CALL k Call subroutine at addre...

Page 58: ...D R A Encoding 0 0011 11rr rrrr Operation A RR Status Affected Z C DC Description Add the contents of the accumulator to data memory R Place the result in R Example ADD 0x10 A add R10 with Acc ADD 0x01 A add R1 with Acc Syntax ADD A k Encoding 1 1111 kkkk kkkk Operation A k A Status Affected Z C DC Description Add the immediate data 8 bit literal to the accumulator Place the result in the accumula...

Page 59: ... 0010 11rr rrrr Operation A R R Status Affected Z Description AND the contents of the accumulator with data memory R Place the result in R Example AND 0x10 A R10 Acc R10 AND 0x01 A R1 Acc R1 Syntax AND A k Encoding 1 1010 kkkk kkkk Operation A k A Status Affected Z Description AND the contents of the accumulator with the immediate data 8 bit literal Place the result in the accumulator Example AND ...

Page 60: ...ister R is set Example BS 0x03 0 set carry flag in Status register BS 0x0C 7 pin 7 of port 2 goes high 5 3 5 CALL Subroutine Call Syntax CALL k Encoding 1 00kk kkkk kkkk Operation PC 1 Top of stack k PC 9 0 R3 7 5 PC 12 10 Status Affected None Description When a subroutine call is invoked the return address is initially pushed into the top of the stack The 10 bit address specified by k is then loa...

Page 61: ...ntents of data memory R are complemented The result is placed in R Example MOV A 0x55 R10 0x55 MOV 0x10 A COM 0x10 R10 0xAA COM 0x0C toggle port 2 5 3 8 COMA Complement R and Place in Acc EM60000 Series User s Manual Instruction Set 53 Syntax COMA R Encoding 0 0100 10rr rrrr Operation R A Status Affected Z Description The contents of data memory R are complemented The result is placed in the accum...

Page 62: ...d produces two 4 bit digits Example Perform a decimal 6 9 operation MOV A 0x6 MOV 0x10 A MOV A 0x9 ADD A 0x10 A 0xF DAA A 15 packed BCD 5 3 10 DEC Decrement R Syntax DEC R Encoding 0 0001 11rr rrrr Operation R 1 R Status Affected Z Description Decrease the contentsof data memory R by one The result is placed in R Example The following codes illustrate how a 16 iteration loop is made MOV A 0x10 R10...

Page 63: ...BS 0x03 2 check Z flag JMP LOOP 5 3 12 DJZ Decrement R Skip if Result is Zero Syntax DJZ R Encoding 0 0101 11rr rrrr Operation R 1 R skip next instruction if the result is zero Status Affected None Description Decrease the contents of data memory R by 1 The result is placed in R If the result is zero the next instruction which is already fetched will be discarded Example The following codes illust...

Page 64: ...R10 Acc DJZA 0x10 Acc R10 1 JMP LOOP if result 0 go to LOOP 5 3 14 GET Get n Bit Width Data from the Voice ROM and Store in Acc Syntax GET n Encoding 0 0000 0010 0nnn Operation n bit width data A Status Affected None Description Get n bit width data from the data stream for speech Channel 1 or 2 and store in the A register n 1 8 The speech channel is determined by R9 The contents of data memory R ...

Page 65: ...atus Affected Z Description The contents of data memory R are increased by one The result is placed in the accumulator Example MOV A 0x5 R10 0x5 MOV 0x10 A INCA 0x10 Acc 0x6 R10 unchanged 5 3 17 IOR Move IOCR to the Acc Syntax IOR R Encoding 0 0000 0001 rrrr Operation IOCR A Status Affected None Description Move data from the I O mapped control register IOCR to the accumulator Example Obtain conte...

Page 66: ...ip next instruction Status Affected None Description If bit b of data memory R is 0 the next instruction which is already fetched will be discarded Example Test Bit 0 of R10 If Bit 0 is 0 Pin 0 of Port 2 is unchanged JBC 0x10 0 BS 0x0C 0 5 3 20 JBS Bit Test Skip if Set Syntax JBS R b Encoding 0 111b bbrr rrrr Operation If R b 1 skip next instruction Status Affected None Description If Bit b of dat...

Page 67: ...EL1 MOV A 0 5 3 22 JZ Increment R Skip if result is zero Syntax JZ R Encoding 0 0111 11rr rrrr Operation R 1 R skip next instruction if result is zero Status Affected None Description Increase the contents of data memory R The result is placed in R If the result is 0 the next instruction which is already fetched is discarded Example The following codes illustrate how to make a 256 iteration loop M...

Page 68: ... Acc R10 1 JMP LOOP if result 0 go to LOOP 5 3 24 MOV Move Data Syntax MOV R A Encoding 0 0000 01rr rrrr Operation A R Status Affected None Description Move the contents of the accumulator to data memory R Example MOV 0x01 A move Acc to TCC R1 MOV 0x10 A move Acc to R10 Syntax MOV R R Encoding 0 0100 01rr rrrr Operation R R Status Affected Z Description Move the contents of data memory to itself I...

Page 69: ...eans R10 0 Syntax MOV A k Encoding 1 1000 kkkk Kkkk Operation k A Status Affected None Description Move the immediate data 8 bit literal to the accumulator Example MOV A 0 move 0 to Acc MOV A 0xFF move 0xFF to Acc 5 3 25 MPY Multiply Syntax MPY R Encoding 0 0000 10rr rrrr Operation R10 R R12 R11 Status Affected None Description Multiply R10 with data memory R The 16 bit result is stored in the R12...

Page 70: ...Status Affected None Description No operation NOP is used for time delay only Example P20 outputs a 1 5 µs pulse system clock 4MHz BS 0x0C 0x0 P20 output high NOP delaying 2 instruction cycles NOP BC 0x0C 0x0 P20 output low 5 3 27 OR Inclusive OR Syntax OR A R Encoding 0 0010 00rr rrrr Operation A R A Status Affected Z Description Inclusive OR the contents of the accumulator with the data memory R...

Page 71: ... Affected Z Description Inclusive OR the contents of the accumulator with the immediate data k 8 bit literal The result is placed in the accumulator Example MOV A 0x55 Acc 0x55 OR A 0xAA Acc Acc 0xAA 0xFF 5 3 28 PAGE Set Page Bits Syntax PAGE n Encoding 0 0000 0011 0nnn Operation n R3 7 5 Status Affected None Description Move immediate data n 3 bit literal into page select bit PS2 PS0 in status re...

Page 72: ...0 RETI Return from Interrupt Syntax RETI Encoding 0 0000 0001 0011 Operation Top of stack PC enable global interrupt Status Affected None Description Return from interrupt routine Stack is popped and the top of the stack is loaded into the PC The global interrupt is enabled Bit 7 of R5 is set Example INT_SR MOV A 0x80 interrupt service routine MOV 0x01 A remember save restore Acc status flag RETI ...

Page 73: ...mmediate data k 8 bit literal is loaded into the accumulator Example Perform a 7 segment LED translation table The 7 segment LED is connected to Port 2 MAIN MOV A 0x10 get the contents of R10 CALL TABLE call table MOV 0x0C A output to 7 segment LED TABLE ADD 0x02 A add PC with Acc RETL 0b11111100 RETL 0b01100000 RETL 0b01100000 RETL 0b11110010 RETL 0b01100110 RETL 0b10110110 RETL 0b10111110 RETL 0...

Page 74: ...plier registers automatically Example SCH1_SR IOR 0x9 speech channel 1 interrupt routine IOW 0x0C read speech data then write to DAC IOW 0x0D RETS Here speech timer 1 interrupt occurs 5 3 33 RLC Rotate Left Through Carry Syntax RLC R Encoding 0 0110 11rr rrrr Operation R n R n 1 carry R 0 R 7 carry Status Affected C Description The contents of data memory R are rotated 1 bit to the left through th...

Page 75: ... left by 1 bit MOV A 05x5 R10 0x55 MOV 0x10 A BC 0x03 0 clear carry bit RLCA 0x10 Acc 0xAA R10 unchanged 5 3 35 RRC Rotate Right through Carry Syntax RRC R Encoding 0 0110 01rr rrrr Operation R n R n 1 carry R 7 R 0 carry Status Affected C Description The contents of data memory R are rotated 1 bit to the right through the carry flag The result is placed in R Example Set carry to 0 first and then ...

Page 76: ... unchanged 5 3 37 SLEP Sleep Syntax SLEP Encoding 0 0000 0000 0011 Operation 0 WDT counter 0 WDT prescaler 0 P 1 T Status Affected P T Description In Status Register the power down bit P is cleared and the time out bit T is set The processor is in SLEEP mode with the oscillator stopped Example SLEP the processor is put into SLEEP mode 5 3 38 SUB Subtract Syntax SUB A R Encoding 0 0001 00rr rrrr Op...

Page 77: ...k A A Status Affected Z C DC Description Subtract the contents of the accumulator from the immediate data 8 bit literal Place the result in the accumulator Example SUB A 100 Acc 100 Acc SUB A 10 Acc 10 Acc 5 3 39 SWAP Swap High Low Nibble Syntax SWAP R Encoding 0 0111 01rr rrrr Operation R 3 0 R 7 4 Status Affected None Description Swap the upper and lower nibbles of data memory R Example MOV A 0x...

Page 78: ...er Syntax WDTC Encoding 0 0000 0000 0100 Operation 0 WDT counter 1 P 1 T Status Affected P T Description Watchdog timer is reset The power down bit P is set The time out bit T is set Example WDTC clear Watchdog Timer counter 5 3 42 XOR Exclusive OR Syntax XOR A R Encoding 0 0011 00rr rrrr Operation A R A Status Affected Z Description Exclusive OR the contents of the accumulator with the data memor...

Page 79: ...le MOV A 0x55 R10 0x55 MOV 0x10 A MOV A 0xAA Acc 0xAA XOR 0x10 A R10 R10 Acc 0xFF Syntax XOR A k Encoding 1 1011 kkkk kkkk Operation A k A Status Affected Z Description Exclusive OR the contents of the accumulator with the immediate data k 8 bit literal The result is placed in the accumulator Example MOV A 0x55 Acc 0x55 XOR A 0xAA Acc Acc 0xAA 0xFF EM60000 Series User s Manual Instruction Set 71 ...

Page 80: ...Chapter 5 72 Instruction Set EM60000Series User s Manual ...

Page 81: ...trol and status registers will be initialized by hardware The initialized conditions are as follows The program counter PC is set to all 0 Bits 5 7 of R3 SF are set to all 0 which means program is set to Page 0 The upper 2 bits of R4 RSR are set to 0 which means RAM Bank 0 is selected R1 TCC R6 MTC and R7 TCC2 are all cleared The count value of watchdog timer and prescaler are cleared R5 INTC Bits...

Page 82: ...ed interrupts from occurring 6 2 1 Example Power on Initialization In the following example the program will initialize the controls and I O function after a reset or as summarize below 1 Go to power on procedure note that the default page is 0 after reset In this example a jump instruction is used directly because the power on procedure is located at address 0x10 in Page 0 Note that if the power ...

Page 83: ...nable Port 1 pull low MOV A 0 set prescaler register to 0 IOW 0x5 CLR 0x4 clear RSR CLR 0xC write 0 to Port 2 CLR 0xD write 0 to Port 3 CLR 0xE write 0 to Port 4 CLR 0xF write 0 to Port 5 MOV A 0 IOW 0xD set Port 2 as output IOW 0xE set Port 3 as output IOW 0xF set Port 4 as output MOV A 0 clear RAM R10 to R1F of Bank 0 MOV 0x4 A CLEAR_RAM CLR 0x0 INC 0x4 MOV A 0x4 XOR A 0x20 JBS 0x3 2 JMP CLEAR_R...

Page 84: ...4 02 MOV A 0x01 MOV 0x13 A R13 01 DJZA 0x13 R13 1 A If A 0 skip JMP OVER else jump over LOOP DJZ 0x14 R14 1 R14 loop 2 times JMP LOOP if R14 0 skip OVER JMP OVER else jump OVER 6 3 2 Example 2 Using JBC JBS BC and BS Instruction about JBC JBS BC and BS ORG 0x0000 JMP POWERON go to power on procedure ORG 0x0010 power on reset procedure POWERON MOV A 0x0F A 0x0F MOV 0x14 A R14 0x0F MOV 0x13 A R13 0x...

Page 85: ...anged by the ALU You should check the resulting status flag register at the end of each operation The following shows which status flags are affected by which instructions Status Flag Instructions that Affect Status Flag Z Zero flag CLR MOV OR AND XOR COM SUB DECA DEC ADD INC INCA C Carry flag RRCA RRC RLCA RLCDAA SUB ADD DC Auxiliary carry flag ADD SUB 6 4 1 Example Applying the AND and COMA Inst...

Page 86: ...P OVER 6 4 3 Example Applying the BC BS SWAPA and SWAP Instructions The routine demonstrates the BC BS SWAPA and SWAP instructions ORG 0x0000 JMP POWERON go to power on procedure ORG 0x0010 power on reset procedure POWERON MOV A 0xEE MOV 0x16 A R16 0xEE BC 0x16 3 set R16 3 0 R16 0xE6 BC 0x16 6 set R16 6 0 R16 0xA6 SWAPA 0x16 R16 3 0 A 7 4 R16 7 4 A 3 0 A 0x6A MOV 0x15 A R15 0x6A SWAP 0x15 R15 3 0 ...

Page 87: ... 0x16 A R16 A R16 13 0x0D MOV A 0x04 A 0x04 ADD A 0x01 A A 1 5 OVER JMP OVER 6 4 5 Example Applying the SUB DEC and DECA Instructions The routine demonstrates the SUB DEC and DECA instructions ORG 0x0000 JMP POWERON go to power on procedure ORG 0x0010 power on reset procedure POWERON MOV A 0x15 MOV 0x15 A R15 0x15 MOV A 0x04 MOV 0x16 A R16 4 SUB A 0x15 A R15 A 0x11 DEC 0x16 R16 3 DEC 0x16 R16 2 DE...

Page 88: ...er on reset you must write an initial value to the port before it is configured as output This will prevent an ambiguous output signal from transpiring especially when output port is used to control external devices like motor or LED 6 5 1 Example Input Pin Polling and Configuring Output Port The example demonstrates input pin polling and output port The system clock Fosc 4MHz Procedure 1 set init...

Page 89: ...0b00000001 MOV 0x0D A p3 0 set to high JMP POLLING go back for polling TR2DEBOUNCE CALL DELAY20 debounce time 20 ms JBS 0x0B 1 detect p1 1 1 Y p3 1 1 JMP POLLING N keep polling TR2 MOV A 0b00000010 MOV 0x0D A p3 1 set to high JMP POLLING go back for polling TR3DEBOUNCE CALL DELAY20 debounce time 20 ms JBS 0x0B 2 detect p1 2 1 Y p3 2 1 JMP POLLING N keep polling TR3 MOV A 0b00000100 MOV 0x0D A p3 2...

Page 90: ...ocedure 1 Set initial value Ports 2 3 as output port 2 Let p2 0 1 detect p1 input or not Y judge trigger N go to 3 3 Let p2 1 1 detect p1 input or not Y judge trigger N go to 4 4 Let p2 2 1 detect p1 input or not Y judge trigger N go to 5 5 Let p2 3 1 detect p1 input or not Y judge trigger N go to 6 6 Reset scan go to 2 ORG 0x0000 JMP POWERON go to power on procedure ORG 0x0010 power on reset proc...

Page 91: ...x13 0 check R13 0 0 JMP PORT21 R13 0 1 go to port21 JBC 0x13 1 check R13 1 0 JMP PORT22 R13 1 1 go to port22 JBC 0x13 2 check R13 2 0 JMP PORT23 R13 2 1 go to port23 JBC 0x13 3 check R13 3 0 JMP PORT20 R13 3 1 go to port20 PORT21 BC 0x03 0 RLC 0x13 left rotate R13 1 1 JMP SCAN PORT22 BC 0x03 0 RLC 0x13 left rotate R13 2 1 JMP SCAN PORT23 BC 0x03 0 RLC 0x13 left rotate R13 3 1 JMP SCAN PORT20 MOV A...

Page 92: ...flag R3 2 0 JMP TR6 R3 2 1 tr6 CALL CHECK9 JBC 0x03 2 check zero flag R3 2 0 JMP TR10 R3 2 1 tr10 CALL CHECK13 JBC 0x03 2 check zero flag R3 2 0 JMP TR14 R3 2 1 tr14 JMP PORT2SCAN TR3DEBOUNCE CALL DELAY20 debounce time 20 ms JBS 0x0B 2 check p1 2 1 JMP PORT2SCAN p1 2 0 port2_scan CALL CHECK1 JBC 0x03 2 check zero flag R3 2 0 JMP TR3 R3 2 1 tr3 CALL CHECK5 JBC 0x03 2 check zero flag R3 2 0 JMP TR7 ...

Page 93: ...16 JMP PORT2 DISPLAY KEYBORD 1 16 TR1 MOV A 0x01 tr1 write 1 to port3 MOV 0x0D A JMP PORT2SCAN TR2 MOV A 0x02 tr2 write 2 to port 3 MOV 0x0D A JMP PORT2_SCAN TR3 MOV A 0X03 tr3 write 3 to port 3 MOV 0x0D A JMP PORT2 TR4 MOV A 0x04 tr4 write 4 to port 3 MOV 0x0D A JMP PORT2 TR5 MOV A 0x05 tr5 write 5 to port 3 MOV 0x0D A JMP PORT2SCAN TR6 MOV A 0x06 tr6 write 6 to port 3 MOV 0x0D A JMP PORT2SCAN TR...

Page 94: ... A JMP PORT2SCAN TR14 MOV A 0x0E tr14 write 0xE to port 3 MOV 0x0D A JMP PORT2SCAN TR15 MOV A 0x0F tr15 write 0xF to port 3 MOV 0x0D A JMP PORT2SCAN TR16 MOV A 0x00 tr16 write 0 to port 3 MOV 0x0D A JMP PORT2SCAN CHECK1 MOV A 0x01 A 1 XOR A 0x13 if R13 XOR A 0 zero flag 1 RET CHECK5 MOV A 0x02 A 2 XOR A 0x13 if R13 XOR A 0 zero flag 1 RET CHECK9 MOV A 0x04 A 4 XOR A 0x13 if R13 XOR A 0 zero flag 1...

Page 95: ...e interrupt functions 6 6 1 TCC Timer Interrupt The TCC Timer interrupt is a general purpose interrupt available for your applications The interrupt source comes from the TCC timer counter overflow the counter is mapped to R1 The interrupt vector is located at program address 0x0002 The interrupt subroutines handle all the contextual switch operation which can be interrupted by the Speech Timer In...

Page 96: ...t program address 0x0002 Like the TCC Timer interrupt the MTC interrupt subroutine handles all the contextual switch operations The subroutine checks R5 INTC for the interrupt flag to determine the type of interrupt currently in use The flag is cleared by program before leaving the interrupt subroutine to avoid recursive interrupts from happening The control method is the same as TCC interrupt con...

Page 97: ... IOW 0xE set port 3 as output setup timer interrupt MOV A 0b00011100 set TCC MTC prescaler bit IOW 0x5 TCC MTC ratio 1 256 MOV A 0x80 set TCC counter initial value MOV 0x01 A MOV A 0xC0 set MTC counter re load value MOV 0x06 A MOV A 0b10001100 enable global and TCC MTC MOV 0x05 A timer interrupts LOOP JMP LOOP idle looping timer interrupt subroutine TCCINT MOV A 0x80 re write TCC counter initial v...

Page 98: ...ss RAM Bank 3 even if the bank has been changed This means that if you change the RAM bank by modifying R4 the RAM address 0x20 0x3F is still mapped to Bank 3 even if the bank select bits have been changed This condition is released after leaving the speech interrupt 3 Like the RAM bank condition the R9 is also forced into the corresponding control register bank speech Channels 1 or 2 Even if you ...

Page 99: ...ch timer interrupt set SPEECH1_SETUP MOV A 0x00 select the speech channel 1 MOV 0x09 A MOV A 0 IOW 0x6 write initial address 0x000000 IOW 0x7 IOW 0x8 IOW 0xB write initial value to DAC registers IOW 0xC MOV A 4000 8 8 8KHz rate 4M 8 8k 62 5 IOW 0x0A write sampling rate BS 0x05 7 enable global interrupt bit ENI BS 0x0A 0 enable speech timer interrupt BS 0x0A 1 enable speech data output to DAC CLR 0...

Page 100: ...9 8 bit format by using the IOR instruction After accessing the address pointer will increase by one automatically The following example shows how to access voice ROM data using the Voice ROM data access control registers 6 7 1 Example Voice ROM Access The example demonstrates how to read the data ROM at about every 65 5ms The data of voice ROM will be displayed on Port 2 ORG 0x0000 JMP POWERON go...

Page 101: ...ails The following steps provides the required procedure 1 Prepare the speech interrupt subroutines 2 Select the DAC control registers by setting R9 set the volume and assign the speech channel then turn on the DAC 3 Select speech Channel 1 or 2 control by setting R9 4 Set up the interrupt interval for correct speech sampling rate write the proper value into the IOCA control register 5 Write the i...

Page 102: ...DAC 1 The program turns off DAC 1 as the last step 6 8 1 Example Simple Speech Playback PCM The example demonstrates PCM speech playback PCM data will be read from voice ROM and output to DAC 1 Assume user has already stored the speech codes 8 bit signed data in the voice ROM System clock is 4MHz speech sampling rate is 8KHz ORG 0x0000 JMP POWERON go to power on procedure ORG 0x000A 0x000A speech ...

Page 103: ...able global INT BS 0x0A 1 enable speech output to DAC BS 0x0A 0 enable speech timer INT speech playback loop WAIT JBS 0x20 4 check active flag in R20 RAM bank 3 JMP WAIT if active flag 1 waiting BC 0x0A 0 else flag 0 disable speech 1 INT BC 0x0A 1 disable speech 1 output to DAC MOV A 0x08 select DAC 1 MOV 0x09 A BC 0x0A 0 turn off DAC 1 OVER JMP OVER speech 1 PCM synthesis subroutine SCH1PCM IOR 0...

Page 104: ...ect the DAC control registers by setting R9 Set the volume and assign the melody channel then turn on the DACs 3 Set the MTC pre scale ratio and counter re load value for desired tempo value 4 Enable the MTC timer interrupt and enter into end of melody wait condition The following example demonstrates a melody playback You have to prepare the interrupt subroutine in advance Once playback starts th...

Page 105: ... of DAC 1 set up tempo MOV A 0xA0 MSR2 0 101 MTC scale 1 64 IOW 0x05 MTC CLK 32us 4MHz 2 64 32us MOV A 216 MTC 216 216 1 32us 6 944 ms MOV 0x06 A MTC timer INT interval 6 944 ms set up melody SETUP_MELODY MOV A 0x02 select voice ROM access control MOV 0x09 A MOV A 0 set melody start data address IOW 0x6 address 0x002000 MOV A 0x20 IOW 0x7 MOV A 0 IOW 0x8 CLR 0x16 R16 store the active flag BS 0x16 ...

Page 106: ...ter value store in beat counter note pitch value store in freq1 2 PLAY TONE MOV A 0x04 select melody channel 1 control MOV 0x09 A MOV A 127 write initial envelope 127 IOW 0xA MOV A wave0 write waveform address wave2 1 0 IOW 0x6 MOV A wave1 IOW 0x7 MOV A wave2 IOW 0x8 MOV A freq1 write frequency value for pitch IOW 0xB MOV A freq2 IOW 0xC BS 0x0A 0 enable tone generator ENVELOPE calculate envelope ...

Page 107: ...wn sleep mode function for energy saving Remember that before going into sleep mode all of the input ports should not be floating to achieve optimum current consumption The following steps describe the sleep and wake up mode process 1 Set up the wake up source 2 Set up the internal pull low control if the wake up is source from Port 1 or Port 2 input pins and no external devices is connected 3 Set...

Page 108: ...A CLR 0x0C set port 2 to 0 CLR 0x0D set port 3 to 0 CLR 0x0E set port 4 to 0 CLR 0x0F set port 5 to 0 MOV A 0 IOW 0xD set port 2 as output IOW 0xE set port 3 as output IOW 0xF set port 4 as output SLEEP_MODE SLEP enter sleep mode COM 0x0C toggle port 2 after wake up JMP SLEEP_MODE 6 10 2 Example Power Down Mode Application for Keyboard Scan The example demonstrates the Keyboard scan with sleep wak...

Page 109: ...an p1 3 JBC 0x0B 3 detect p1 3 1 Y tr4_debounce JMP TR4_DEBOUNCE N scan JMP SCAN TR1_DEBOUNCE CALL DELAY20 debounce time 20 ms JBS 0x0B 0 detect p1 0 1 Y p3 0 1 JMP SCAN N scan TR1 MOV A 0b00000001 MOV 0x0D A SLEP enter sleep mode JMP INIT wake up and go to INIT TR2_DEBOUNCE CALL DELAY20 debounce time 20 ms JBS 0x0B 1 detect p1 1 1 Y p3 1 1 JMP SCAN N scan TR2 MOV A 0b00000010 MOV 0x0D A SLEP ente...

Page 110: ...0001000 MOV 0x0D A SLEP enter sleep mode JMP INIT wake up and go to INIT delay subroutine for Fosc 4MHz total delay 1 1 200 200 200 100 200 100 200 200 0 5us 20 4ms DELAY20 MOV A 200 1 cycle MOV 0x14 A 1 cycle DL20 MOV A 100 200 cycles MOV 0x15 A 200 cycles DL21 DJZ 0x15 200 100 cycles JMP DL20 200 100 cycles DJZ 0x14 200 cycles JMP DL21 200 cycles RET 102 Software Application EM60000Series User s...

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