EKF PC7-FESTIVAL, User Manual

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User Guide • PC7-FESTIVAL • CompactPCI® PlusIO CPU Board
Read/Clear Status Register 0
Write: SMBus Address 0xB0
Read: SMBus Address 0xB1
Bit Description CMD_STAT0
7 PF18S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.8S voltage regulator
6 PF10S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.0S voltage regulator
5 PF10A
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.0A voltage regulator
4 PF25S4
0=Normal operation
1=Last system reset may be caused by a power failure of the +V2.5S4 voltage regulator
3 PF12S4
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.2S4 voltage regulator
2 PFVRST
0=Normal operation
1=Last system reset may be caused by a power failure of the +VCCST load switch
1 PFVRIO
0=Normal operation
1=Last system reset may be caused by a power failure of the +VCCIO voltage regulator
0 PFVRC
0=Normal operation
1=Last system reset may be caused by a power failure of the IMVP-8 voltage regulator
The bits in this register are sticky, i.e. their state will be kept even if a system reset occurs. To clear
the bits a write to the register with arbitrary data may be performed.
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