Chapter 3
H61H2-TI USER MANUAL
48
Read CAS# Precharge(tRTP) (5)
This item controls the Read to precharge delay for memory devices, in memory clock
cycles.
Four Active Window Delay(tFAW) (20)
This item controls the four bank activate time in memory clock cycles.
Press <Esc> to return to the Frequency/Voltage Menu page.
Chipset OverClocking Configuration
Scroll to this item to view the following screen:
Main
Advanced Chipset
Frequency/Voltag
Boot Security Exit
Memory Timing Cofiguration
CAS# Latency(tCL)
9
RAS# to CAS# Delay(tRCD)
9
Row Precharge Time(tRP)
9
RAS# Active Time(tRAS)
24
Write Recovery Time(tWR)
10
Row Refresh Cycle Time(tRFC)
74
Active to Active Delay(tRRD)
4
Write to Read Delay(tWTR)
5
Read CAS# Precharge(tRTP)
5
Four Active Window Delay(tFAW)
20
CAS# Latency(tCL) (9)
This item determines the operation of DDR SDRAM memory CAS (column address
strobe). It is recommended that you leave this item at the default value. The 2T
setting requires faster memory that specifically supports this mode.
RAS# to CAS# Delay(tRCD) (9)
This item specifies RAS# to CAS# delay to Rd/Wr command to the same bank.
Row Precharge Time(tRP) (9)
This item specifies Row precharge to Active or Auto-Refresh of the same bank.
RAS# Active Time(tRAS) (24)
This item specifies the RAS# active time.
Write Recovery Time(tWR) (10)
This item specifies the write recovery time.
Row Refresh Cycle Time(tRFC) (74)
This item specifies the row refresh cycle time.
Active to Active Delay(tRRD) (4)
This item controls the active bank x to active bank y in memory clock cycles.
Write to Read Delay(tWTR) (5)
This item specifies the write to read delay time.
+/- : Change Opt.
Enter : Select
: Select Screen
: Select Item
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC : Exit
