ECS 649-M2, Manual, Page: 41 / 98

35
Using BIOS
Advanced Chipset Features
These items define critical timing parameters of the motherboard. You should leave the
items on this page at their default values unless you are very familiar with the technical
specifications of your system hardware. If you change the values incorrectly, you may
introduce fatal errors or recurring instability into your system.
DRAM Clock/Drive Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
DDR CAS Latency (SPD)
This item controls the timing delay (in clock cycles) before the DRAM starts a read
command after receiving it.
DRAM Timing Control (Auto)
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The value is set at
the factory depending on the DRAM installed. Do not change the values in this field
unless you change specifications of the installed DRAM or the installed CPU.
• RAS to CAS Delay (tRCD) (2T): This is the amount of time a CAS is per-
formed after a RAS. The lower the better, but some DRAM does not support
low figures.
DRAM Clock/Drive Control [Press Enter]
System BIOS Cacheable
[Disabled]
Video RAM Cacheable [Disabled]
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
Advanced Chipset Features
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
DDR CAS Latency [By SPD]
DRAM Timing Control [Auto]
RAS to CAS Delay (tRCD) 2T
Precharge Time (tRP) 2T
RAS Active Time (tRAS) 15T
Write Recovery Time (tWR) 1T
Command Bypass [Disabled]
Data Bypass [Disabled]
UMC0 MA Timing [Auto]
UMC0 Read Data Ready [Auto]
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
x
x
x
x
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help