EarthWalk eBuddy Series 3, User Manual, Page: 77 / 99

Chapter 5: BIOS setup
eBuddy User Manual -68- 2/4/00
DRAM Read Burst (EDO/FP)
This sets the timing for burst mode reads from two different DRAM (EDO/
FPM). Burst read and write requests are generated by the CPU in four separate
parts. The first part provides the location within the DRAM where the read or
write is to take place. The remaining three parts provide the actual data. The
lower the timing numbers, the faster the system will address memory:
x222/x333 Read DRAM (EDO/FPM) timings are 2-2-2/3-3-3
x333/x444 Read DRAM (EDO/FPM) timings are 3-3-3/4-4-4
DRAM Write Burst Timing
This sets the timing for burst mode writes from DRAM. Burst read and write
requests are generated by the CPU in four separate parts. The first part provides
the location within the DRAM where the read or write is to take place. The
remaining three parts provide the actual data. The lower the timing numbers,
the faster the system will address memory:
x222 Write DRAM timings are 2-2-2-2
x333 Write DRAM timings are 3-3-3-3
Fast EDO Lead Off
The default value is Disabled.
Refresh RAS# Assertion
The options are 4 Clks or 5 Clks.
Fast RAS to CAS Delay
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from Row
Address Strobe (RAS) to Column Address Strobe (CAS). Options are as fol-
lows:
3 Three CPU clock delay
2 Two CPU clock delay
ebud.book Page 68 Friday, February 4, 2000 11:11 AM