® 8k/4k CL
24
UM 8k/4k CL – REVA – 01/13
e2v semiconductors SAS 2013
•
Output Frequency
(
OutputFrequency
) :
Set the CameraLink Data Output Frequency. This value is available in
the CommCam “Image Format Control” section :
Read function : “
r clfq
”;
Return by the Camera : Frequency from 0 to 5
Write Function : “
w clfq
<value>”
“0” : 85MHz (default).
“1” : 60MHz.
“2” : 65MHz.
“3” : 70MHz.
“4” : 75MHz.
“5” : 80MHz.
Data Output Frequency Reduction
The Purpose of this feature is to optimize (increase) the Length of the Cable when highest
Line Rate is not required. Each decreasing of the Data Frequency will increase the minimum
Line Period possible, this depending also on the Binning mode (number of pixels outputted from
8192 to 2048
Structure of the Sensor
In 2S Mode, the summation of the
two lines is done in the FPGA :
B+C
In 4S Mode, the summation of the
two double lines is done in the
FPGA :
(AB )+ (BC)
This mode works in “Time delay
exposure” for the summation of
each double line in the sensor.
ADC
ADC
Memory Node
Pixel Line A
Pixel Line B
Pixel Line C
Pixel Line D
Memory Node
Web Direction
2S
1S
4S
Exposure
delays
FPGA