E-peas AEM10941 User Manual Download Page 7

User guide

AEM10941

User guide

AEM10941

User guide

AEM10941

How to reset the AEM10941 evaluation board:

To reset the board, simply

disconnect the storage device and the optional primary battery

and connect the 6 ”Reset”

connections (working from the rightmost to the left) to a

GND

node (i.e. the negative pin of any connector) in order to

discharge the internal nodes of the system.

3

Functional Tests

This section presents a few simple tests that allow the user
to understand the functional behavior of the AEM10941.

To

avoid damaging the board, follow the procedure found in Sec-
tion 2.1 ”Safety information”.

If a test has to be restarted,

make sure to properly reset the system to obtain reproducible
results.
The following functional tests were made using the following
setup:

- Configuration:

SELMPP[1:0]

= LL,

CFG[2:0]

= HLL,

ENLV

= H,

ENHV

= H

- Storage element: capacitor (4

.

7 mF + CBATT)

- Load: 10 kΩ on

HVOUT

,

LVOUT

floating

-

SRC

: current source (1 mA or 100

µ

A) with voltage com-

pliance (4 V)

Feel free to adapt the setup to match your system as long as
you respect the input and cold-start constraints (see Section
1 ”Introduction” of AEM10941 datasheet).

3.1

Start-up

The following example allows users to observe the behavior of
the AEM10941 in the wake-up mode.

Setup

1. Place the probes on the nodes to be observed.

2. Referring to Figure 1, follow steps 1 to 5 explained in

Section 2.1.

Observations and measurements

-

BATT

: Voltage rises as the power provided by the source

is transferred to the storage element (see Figure 2).

-

SRC

: Regulated at

Vmpp

, which is a voltage equal to the

open-circuit voltage (

Voc

) times the MPP ratio defined

in Table 4.

Vsrc

equals

Voc

during MPP evaluation (see

Figure 3). Note that

Vsrc

must be higher than 380 mV

to coldstart.

-

HLDO

/

LLDO

: Regulated when voltage on

BATT

first

rises above

Vchrdy

(see Figure 2).

-

STATUS[0]

: Asserted when the LDOs are ready to be

enabled (refer to Section 7.2 ”Normal mode” of the
AEM10941 datasheet) (see Figure 2).

-

STATUS[2]

: Asserted each time the AEM10941 per-

forms a MPP evaluation (see Figure 3).

0

5

10

15

20

0

1

2

Vchrdy

Time [s]

V

o

lt

ag

e

[V

]

BATT

STATUS[0]

HLDO

Figure 2:

STATUS[0]

and

HLDO

evolution with

BATT

0

5

10

15

20

0

1

2

3

4

Vmpp

Voc

5s

Time [s]

V

o

lt

ag

e

[V

]

STATUS[2]

SRC

Figure 3:

SRC

and

STATUS[2]

while energy is ex-

tracted from

SRC

(

BATT

under

Vovch

)

7

UG AEM10941 REV1.0

Copyright c

2018 e-peas SA

7

UG AEM10941 REV1.0

Copyright c

2018 e-peas SA

7

UG AEM10941 REV1.0

Copyright c

2018 e-peas SA

Summary of Contents for AEM10941

Page 1: ...e design of a highly efficient solar energy powered subsystem in your target appli cation Applications PV cell harvesting Home automation Industrial monitoring E health monitoring Geolocation Wireless sensor nodes Appearance Features Four two way screw terminals Source of energy PV cell Low voltage load High voltage load Primary energy storage element One three way screw terminal Energy storage el...

Page 2: ...3 2 STATUS 0 and HLDO evolution with BATT 7 3 SRC and STATUS 2 while energy is extracted from SRC BATT under Vovch 7 4 LDOs disabled around 600 ms after BATT reaches Vovdis 8 5 Switching from SRC to the primary battery 8 6 AEM10941 behaviour during cold start 9 7 HVOUT at 2 5V 10 8 Boost efficiency for ISRC 1 mA 11 9 PV cell first order model 12 10 Typical I V curve of a PV cell for high and low i...

Page 3: ...not used MPP con gura on Mandatory connec on See Table 4 Ba ery LDOs con gura on Mandatory connec on See Table 2 LDOs enabling Mandatory connec on See Table 3 Cold start con gura on Mandatory connec on Connect a jumper to FB_COLD 2 pins or use the resistors See Sec on 2 3 3 PV Cell Warning Please refer to Sec on 2 1 before connec ng the board A 150 µF capacitor CBATT is already soldered on BATT Hi...

Page 4: ...Connect a jumper to each NoPRIM 2 pins FB HV Configuration of the high voltage LDO in the cus tom mode Use resistors R5 R6 see Section 2 3 1 Leave floating FB COLD Configuration of the cold start Use resistors R9 R10 see Section 2 3 3 Connect a jumper to FB COLD 2 pins if not used Configuration of the threshold voltages for the energy storage element and the output voltage of the LDOs Connect jump...

Page 5: ... is not available on the AEM10941 evaluation board The MPP is by default configured to 50 of Voc as this ratio optimize the proposed rectifier efficiency Configuration pins Storage element threshold voltages LDOs output voltages Typical use CFG 2 CFG 1 CFG 0 Vovch Vchrdy Vovdis Vhv Vlv H H H 4 12 V 3 67 V 3 60 V 3 3 V 1 8 V Li ion battery H H L 4 12 V 4 04 V 3 60 V 3 3 V 1 8 V Solid state battery ...

Page 6: ...f unused leave the resistor footprints R1 to R6 empty 2 3 2 Primary battery configuration As to the main storage element the primary battery protection levels have to be defined To do so use resistors R7 R8 By defining RP R7 R8 100 kΩ RP 500 kΩ R7 Vprim min 4 RP 2 2 V R8 RP R7 If unused connect a jumper to each NoPRIM 2 pins 2 3 3 Cold start configuration The cold start voltage i e the voltage nee...

Page 7: ...f AEM10941 datasheet 3 1 Start up The following example allows users to observe the behavior of the AEM10941 in the wake up mode Setup 1 Place the probes on the nodes to be observed 2 Referring to Figure 1 follow steps 1 to 5 explained in Section 2 1 Observations and measurements BATT Voltage rises as the power provided by the source is transferred to the storage element see Figure 2 SRC Regulated...

Page 8: ... 1 follow steps 1 to 5 explained in Section 2 1 Configure the board in the desired state and start the system see Section 3 1 Connect a primary battery example 3 1 V coin cell with protection level at 2 4 V R7 68 kΩ and R8 180 kΩ 3 Let the system reach a steady state i e voltage on BATT between Vchrdy and Vovch and STATUS 0 as serted 4 Remove your source element and let the system dis charge throu...

Page 9: ...upercapacitor balancing circuit This test allows users to observe the balancing circuit behavior that maintains the voltage on BAL equilibrated Setup 1 Following steps 1 and 2 explained in Section 2 1 and re ferring to Figure 1 configure the board in the desired state Plug the jumper linking BAL to ToCN 2 BATT Plug capacitor C1 between the positive and the BAL pins and a capacitor C2 between BAL a...

Page 10: ...e a voltage between Vovch and 5 V on SMU1 to force the AEM to start 2 Sweep voltage on SMU1 from Vovdis 50 mV to 4 5 V 3 Repeat with different current levels on SMU2 from 10 µA to 80 mA for HVOUT and from 10 µA to 20 mA for LVOUT Measurements HVOUT LVOUT Measure the voltage 3 3 5 4 4 5 2 3 2 4 2 5 2 6 VBOOST V VHVOUT V IHVOUT 10 µA IHVOUT 10 mA IHVOUT 80 mA Figure 7 HVOUT at 2 5V 4 2 BOOST efficie...

Page 11: ...ct CFG 2 0 LLL to select cus tom mode and choose R1 to R6 to configure the battery protection levels and HVOUT output voltage 2 Place the probes on the nodes to be observed 3 SRC Connect your source element to start the flow of power to the system Manipulations 1 Remove the source element after the voltage on BATT has reached steady state between Vchrdy and Vovch Measurements Measure the following...

Page 12: ...age curves can be drawn as shown in Figure 11 For a given technology the max imum extracted power is achieved at a voltage corresponding to a given ratio of the open circuit voltage between 70 and 90 This ratio is in first approximation independent of the illumination level as can be seen in Figure 11 Vmpp Voc Vmpp Voc As presented in Table 4 the MPP configuration of the AEM10941 allows you to sel...

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