CIRCUIT DESCRIPTION
4-4
December 1997
Part No. 001-7500-001
Figure 4-3 PLL Circuit
Buffers
Q5, Q26
4.3 PLL CIRCUIT
A PLL circuit shown in Figure 4-3 provides a sta-
ble transmit frequency and receive first LO fre-
quency. The PLL output compares the phase of the
divided VCO frequency to the reference frequency.
The PLL output frequency is controlled by the divided
ratio (N-data) of a programmable divider.
The PLL circuit includes VCO Q7 and Q8. The
VCO signal is amplified by buffer-amplifiers Q5 and
Q6 and then applied to PLL integrated circuit IC1 on
pin 2.
The PLL integrated circuit contains a prescaler,
programmable counter, phase detector, charge pump,
and other circuits. The input signal is divided by the
prescaler and programmable counter by the N-data
from the CPU. The phase of the divided signal is
detected in relation to the reference frequency by the
phase detector.
If the VCO frequency begins drifting, the phase
changes from that of the reference frequency. The
control voltage then changes to compensate for this
frequency drift.
Part of the VCO signal is amplified by buffer-
amplifier Q4 and applied to the receive first mixer or
transmit buffer-amplifier circuit via T/R switching
diodes D3 and D4.
4.4 POWER SUPPLY CIRCUITS
Voltage Line
Line
Description
HV
The voltage of the attached battery pack.
Vcc
The same voltage as HV (battery). It is switched
by the power switch.
CPU5 Common 5V converted from the Vcc line by reg-
ulator IC6. The output voltage is applied to CPU
IC8 and the 5V regulator circuit.
5V
Common 5V supply converted from the Vcc line
by 5V regulator circuit Q18 and Q19 using a ref-
erence provided by CPU5 regulator IC6.
T5
A 5V supply enabled only in the transmit mode
and regulated by Q22.
R5
A 5V supply enabled only in the receive mode
and regulated by Q21.
S5
Common 5V supply converted from the 5V line
by regulator Q20 for the synthesizer.