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Chapter 2 – Related Documents

CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual

2. Related

Documents

Listed below are documents that describe the Pentium processor and chipset, and the peripheral components used on
the XPD. Either download from the Internet or contact your local distributor for copies of these documents.

The XPD uses the L2400 Low Voltage Core Duo. For information on this processor, go to:

http://ark.intel.com/products/28026?wapkw=l7400

For the ICH component in the 6300ESBchipset get the

Intel

6300ESB I/O Controller Hub Datasheet

. It is document

number 300641-002.

ftp://download.intel.com/design/intarch/datashts/30064102.pdf

For information on the E7520 MCH component in the chipset, please go to:

http://www.intel.com/design/chipsets/embedded/e7520_7320.htm

For data sheets on I/O controllers:



82571EB Fast Ethernet PCI Controller

http://www.intel.com/design/network/products/lan/controllers/82571eb.htm



VMEbus Interface Components Manual

Tundra Semiconductor Corporation; Universe IID revisions are found at www.tundra.com

The following documents provide information on the PC architecture and I/O:



PCI Local Bus Specification, Revision 2.2

http://www.pcisig.com/specifications/



PCI-X Specification, Revision 1.0A

http://www.pcisig.com/specifications/



System Management Bus Specification (SMBus), Revision 1.1

http://www.smbus.org/specs/



Universal Serial Bus Specification

http://www.usb.org/developers

The following documents cover topics relevant to the VMEbus and can be purchased through VITA:



IEEE Std 1014-1987,

IEEE Standard for a Versatile Backplane Bus: VMEbus

The Institute of Electrical and Electronic Engineers
345 East 47th Street
New York, NY 10017
(800) 678-4333



Wade D. Peterson,

The VMEbus Handbook

VITA
10229 North Scottsdale Road, Suite B
Scottsdale, AZ 85253
(480) 951-8866

Summary of Contents for CPU-71-10

Page 1: ...USER MANUAL CPU 71 10 DPD RPD XPD VMEbus Intel Core Duo Single Board Computer DPDMAN103A Updated 14 Dec 2012 ...

Page 2: ...CPU 71 10 XPD User s Manual Rev 1 03 Revised to fix JP8 description December 2012 Dynatem 23263 Madero Suite C Mission Viejo CA 92691 Phone 949 855 3235 Fax 949 770 3481 www dynatem com ...

Page 3: ...ics Processor 8 3 7 Tundra Universe IID CA91C142D PCI VMEbus Interface 9 3 8 PCI Mezzanine Card PMCX and XMC Expansion 12 3 9 Intel s FW82802A Firmware Hub Holds the System BIOS In Flash Memory 12 3 10 Clock Drivers 12 3 11 Reset Circuitry 13 3 12 Watchdog Timer Operation 14 4 Installation 15 4 1 Jumper Selectable Options 15 4 2 CompactFlash Drive Installation 17 4 3 PCI Mezzanine Card PMC Install...

Page 4: ...1 JN2 JN3 and JN4 and XMC Connector J15 25 B BIOS Setup 31 B 1 Redirecting to a Serial Port 31 B 2 Setup Menus 31 B 3 Navigating Setup Menus Fields 32 B 4 Main Setup Menu 33 B 5 Exit Setup Menu 34 B 6 Boot Setup Menu 35 B 7 POST Setup Menu 37 B 8 PnP Setup Menu 39 B 9 Super I O SIO Setup Menu 40 B 10 Features Setup Menu 41 B 11 Firmbase Setup Menu 42 B 12 Miscellaneous Setup Menu 44 C Power and En...

Page 5: ... When referring to attributes of both versions we will use the common name XPD The XPD employs Intel s embedded technology to assure long term availability Features of the XPD include A 1 5 GHz Intel Core2 Duo L7400 processor with 4 MB of L2 cache Single slot VMEbus operation with on board CompactFlash disk for bootable mass storage and front panel connectors for two USB 2 0 ports two Fast Etherne...

Page 6: ...provided on board Tundra Universe IID PCI VMEbus Interface provides 64 bit VMEbus transfer rates over 30 MB sec Integral FIFOs permit write posting to maximize available PCI and VMEbus bandwidth Full Slot 1 System Controller functionality is provided PCI Mezzanine Card PMC expansion supports 64 bits up to 66 MHz A second PCI Mezzanine Card PMC expansion supports 64 bits up to 66 MHz and can also s...

Page 7: ...a sheets on I O controllers 82571EB Fast Ethernet PCI Controller http www intel com design network products lan controllers 82571eb htm VMEbus Interface Components Manual Tundra Semiconductor Corporation Universe IID revisions are found at www tundra com The following documents provide information on the PC architecture and I O PCI Local Bus Specification Revision 2 2 http www pcisig com specifica...

Page 8: ...ne Card Family CMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 IEEE Draft Std P1386 1 2 0 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 VITA 42 0 XMC Switched Mezzanine Card Auxiliary Standard VITA 10229...

Page 9: ...ion CPU 71 10 XPD RPD DPD VMEbus Core 2 Duo Processor Board User s Manual 5 3 Hardware Description 3 1 Overview The block diagram of the XPD is shown below The sections that follow describe the major functional blocks of the XPD ...

Page 10: ...k cycle Together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 5 33 GB second 3 3 Chipset The Intel E7520 Memory Controller Hub MCH and Intel 6300ESB I O Controller Hub ICH chipset provide memory control mass storage and basic I O and standard PC system resources including the real time clock NV RAM timers thermal management and interrupt management Also the MCH provides...

Page 11: ...sible from the front panel The 82571EB is a single compact component with two fully integrated Gigabit Ethernet Media Access Control MAC and physical layer PHY ports This device uses the PCI Express architecture Rev 1 0a and also enables a dual port Gigabit Ethernet implementation in a very small area which is useful for embedded designs with critical space constraints The Intel 82571EB Gigabit Et...

Page 12: ...net ports are brought to industry standard RJ 45 connectors on Dynatem s rear I O plug in module XPDPTB The two Ethernet ports provided by the DPD s 2nd 82571EB are accessible from the front panel Technical documents on Intel s 82571EB Dual Gigabit Ethernet Controller are available at http www intel com design network products lan docs 82571eb_docs htm 3 6 Silicon Motion SM712 Graphics Processor T...

Page 13: ...ble DMA controller with linked list support Full VMEbus system controller functionality Complete VMEbus address and data transfer modes A32 A24 A16 master and slave D64 MBLT D32 D16 D08 master and slave The block diagram of the PCI VMEbus interface is shown below PCI VMEbus Interface Block Diagram VMEbus P1 Connector VMEbus P2 Connector Reset Circuitry I O Controller Hub ICH Universe IID CA91C142D...

Page 14: ...le from www tundra com which contains comprehensive descriptions of the operation and programming of the Universe IID That manual provides the necessary information to understand the operating modes of the Universe IID XPD initiated transfers PCI slave VMEbus master Other VMEbus master initiated transfers PCI master VMEbus slave DMA controller transfers PCI master VMEbus master VMEbus interrupt ge...

Page 15: ...A16 Base Address BS 31 12 in Table A 77 Lowest address in the 4 KB slave image Slave Image Enable EN in Table A 76 Enable VMEbus Register Access Image Mode SUPER in Table A 76 Supervisor and or Non Privileged Type PGM in Table A 76 Program and or Data The reset state of the VAS BS 31 12 and EN fields can be configured as power up options On the XPD all of these fields reset to 0 Thus the VRAI meth...

Page 16: ... MB of memory is aliased from FFF00000 FFFFFFFF where it can be fully accessed after booting up through the BIOS Here s a link to a datasheet for the 82802AC ftp download intel com design chipsets datashts 29065804 pdf 3 10 Clock Drivers The clock driver circuitry is shown below The clocks are generated by the 932S208 which is driven by a 14 31818 MHz crystal DRAM clocks are synthesized by the MCH...

Page 17: ...VCSR_SET RESET MISC_CTL SW_LRST MISC_CTL SW_SYSRST PWRRST VRSYSRST VXSYSRST LRST Pull up Front Panel Reset Switch 5 VDC Monitor Reset Registers State Machines Core Duo soft reset PCI peripherals Core Duo hard reset VMEbus SYSRESET INIT PCIRST SYSRESET Reset Control Register PB1 General Purpose Output Register s GPIO20 Watchdog Strobe NAND Gate WDT_CLKEN JP4 14 318 MHz Clock Open Drain Buffer 3 3V ...

Page 18: ...the XPD without asserting a VMEbus SYSRESET signal Another VMEbus master sets the RESET bit in the VCSR_SET register of the Universe IID over the VMEbus In this case the LRST signals remains asserted until the RESET bit of the VCSR_CLR register of the Universe IID is set by another VMEbus master over the VMEbus The Reset Control Register in the ICH can be set appropriately by code running on the X...

Page 19: ...1 Selectable Options This section explains how to set up user configurable jumpers and how to install CompactFlash drives and PMC modules The XPD is shipped in an antistatic bag Be sure to observe proper handling procedures during the configuration and installation process to avoid damage due to electrostatic discharge ESD The XPD contains eight jumpers JP3 is located near JN1 for the second PMC s...

Page 20: ...bus Open XPD Drives SYSRESET to the VMEbus Closed VMEbus SYSRESET Out Selection When a VMEbus module occupies slot 1 of the VMEbus chassis the slot to the extreme left it must operate as system controller act as multiprocessing arbiter and generate utility bus signals JP1 configures the VMEbus System Controller functionality of the Universe IID as shown below VMEbus System Controller JP1 Enabled O...

Page 21: ... Data Rates with VIO 3 3 V JP3 is shunted between pins 1 2 1 2 33 MHz 33 MHz and 66 MHz The General Software BIOS will determine during startup what the status of the PCI X bus The BIOS monitors the following pins that are routed to the ICH PCIXCAP PCX X capable and M66EN 66 MHz capable The user s manual on your PMC X modules will tell you how PCIXCAP JN1 pin 39 and M66EN JN2 pin 47 are configured...

Page 22: ...he XPD into the VMEbus connectors on the chassis Tighten the screws to the outside of the ejector handles to complete the installation of the XPD in the VMEbus chassis 4 5 Front Panel Connectors and Reset Switch The XPD offers front panel connections for two USB ports and two RJ45 connector for 1000BaseTX Ethernet ports Install all front panel cables by inserting them into the appropriate connecto...

Page 23: ... of the XPD connectors are shown below The connectors that do not go to the front panel have their pin 1 location designated accordingly 82571EB Dual Gb LAN VMEbus P2 USB0 1 VMEbus P1 Core Duo MCH ICH VMEbus P0 Two 1Gb LAN Ports J1 Universe CompactFlash J3 PMC Connectors J21 J22 J23 J24 XMC Connector Reset Button J11 J12 J13 J14 A B J15 ...

Page 24: ...SB Connectors USB1 USB2 Front Panel USB Receptacles The metal shell of the connector goes to chassis ground A 2 1000BaseTX Fast Ethernet Front Panel Connector J1 The XPD uses a dual RJ45 connector to provide two 1000BaseTX Ethernet ports at the front panel Though there are two separate ports in one connector the pin outs are identical so the following table offers the pin out of one connector as b...

Page 25: ... D7 31 D15 7 CS1 32 CS3 8 GND 33 No connection 9 GND 34 DIOR 10 GND 35 DIOW 11 GND 36 5 VDC 12 GND 37 DIRQ IRQ15 13 5 VDC 38 5 VDC 14 GND 39 Pulled Low master 15 GND 40 No connection 16 GND 41 IDERESET 17 GND 42 Pulled Up to 3 3 VDC 18 DA2 43 No connection 19 DA1 44 5 VDC 20 DA0 45 No connection 21 D0 46 Pull up to 5 VDC 22 D1 47 D8 23 D2 48 D9 24 No connection 49 D10 25 No connection 50 GND Compa...

Page 26: ...RST D12 NC Z13 NC A13 DS0 B13 BR1 C13 LWORD D13 GA2 Z14 GND A14 WRITE B14 BR2 C14 AM5 D14 NC Z15 NC A15 GND B15 BR3 C15 A23 D15 GA3 Z16 GND A16 DTACK B16 AM0 C16 A22 D16 NC Z17 NC A17 GND B17 AM1 C17 A21 D17 GA4 Z18 GND A18 AS B18 AM2 C18 A20 D18 NC Z19 NC A19 GND B19 AM3 C19 A19 D19 NC Z20 GND A20 IACK B20 GND C20 A18 D20 NC Z21 NC A21 IACKIN B21 No connection NC C21 A17 D21 NC Z22 GND A22 IACKOU...

Page 27: ... 13 Z10 GND A10 PDDACK B10 A30 C10 PDIOW D10 P14 15 Z11 P14 17 A11 IRQ14 B11 A31 C11 PDIOR D11 P14 16 Z12 GND A12 PDA1 B12 GND C12 PDA2 D12 P14 18 Z13 P14 20 A13 PDA0 B13 5 VDC C13 PDCS3 D13 P14 19 Z14 GND A14 PDCS1 B14 D16 C14 USB_3N D14 P14 21 Z15 P14 23 A15 BIT_OUT1 B15 D17 C15 USB_3P D15 P14 22 Z16 GND A16 BIT_OUT0 B16 D18 C16 PRI_RST D16 P14 24 Z17 P14 26 A17 BIT_CNTRL1 B17 D19 C17 USB_2N C17...

Page 28: ...D03 LPa_DD E03 LPa_DD A04 LPb_DA B04 LPb_DA C04 VGA_HSYNC D04 LPb_DC E04 LPb_DC A05 LPb_DB B05 LPb_DB C05 VGA_VSYNC D05 LPb_DD E05 LPb_DD A06 SATA1_RXN B06 SATA1_RXP C06 VGA_ddcdata D06 SATA0_RXN E06 SATA0_RXP A07 PIO5 B07 PIO4 C07 PIO3 D07 PIO2 E07 PIO1 A08 PIO10 B08 PIO9 C08 PIO8 D08 PIO7 E08 PIO6 A09 PIO15 B09 PIO14 C09 PIO13 D09 PIO12 E09 PIO11 A10 PIO20 B10 PIO19 C10 PIO18 D10 PIO17 E10 PIO16...

Page 29: ... these pinouts will be provided separately Pin Signal Pin Signal 1 5 6K pull down 2 12 VDC 3 GND 4 PX_PIRQ0 PX_PIRQ1 5 PX_PIRQ1 PX_PIRQ2 6 PX_PIRQ2 PX_PIRQ3 7 No connection 8 5 VDC 9 PX_PIRQ3 PX_PIRQ0 10 No connection 11 GND 12 No connection 13 PMC1CLK PMC1CLK 14 GND 15 GND 16 GNT0 GNT1 17 REQ0 REQ1 18 5 VDC 19 VI O from JP3 20 AD31 21 AD28 22 AD27 23 AD25 24 GND 25 GND 26 C BE3 27 AD22 28 AD21 29...

Page 30: ...tion 18 GND 19 AD30 20 AD29 21 GND 22 AD26 23 AD24 24 3 3 VDC 25 IDSEL AD17 AD18 26 AD23 27 3 3 VDC 28 AD20 29 AD18 30 GND 31 AD16 32 C BE2 33 GND 34 No connection 35 TRDY 36 3 3 VDC 37 GND 38 STOP 39 PERR 40 GND 41 3 3 VDC 42 SERR 43 C BE1 44 GND 45 AD14 46 AD13 47 M66EN 48 AD10 49 AD8 50 3 3 VDC 51 AD7 52 No connection 53 3 3 VDC 54 No connection 55 No connection 56 GND 57 No connection 58 No co...

Page 31: ...AD59 18 AD58 19 AD57 20 GND 21 VIO 22 AD56 23 AD55 24 AD54 25 AD53 26 GND 27 GND 28 AD52 29 AD51 30 AD50 31 AD49 32 GND 33 GND 34 AD48 35 AD47 36 AD46 37 AD45 38 GND 39 VIO 40 AD44 41 AD43 42 AD42 43 AD41 44 GND 45 GND 46 AD40 47 AD39 48 AD38 49 AD37 50 GND 51 GND 52 AD36 53 AD35 54 AD34 55 AD33 56 GND 57 VIO 58 AD32 59 No connection 60 No connection 61 No connection 62 GND 63 GND 64 No connection...

Page 32: ...37 D25 38 Z25 39 D26 40 D27 41 Z27 42 D28 43 D29 44 Z29 45 D30 46 Z31 47 No connection 48 No connection 49 No connection 50 No connection 51 No connection 52 No connection 53 No connection 54 No connection 55 No connection 56 No connection 57 No connection 58 No connection 59 No connection 60 No connection 61 No connection 62 No connection 63 No connection 64 No connection PCI X Mezzanine Card PMC...

Page 33: ...B11 25 A11 26 E12 27 D12 28 C12 29 B12 30 A12 31 E13 32 D13 33 C13 34 B13 35 A13 36 E14 37 D14 38 C14 39 B14 40 A14 41 E15 42 D15 43 C15 44 B15 45 A15 46 E16 47 D16 48 C16 49 B16 50 A16 51 E17 52 D17 53 C17 54 B17 55 A17 56 E18 57 D18 58 C18 59 B18 60 A18 61 E19 62 D19 63 C19 64 B19 PCI X Mezzanine Card PMCX Site 2 Connector J24 Molex 71439 0164 J24 is the JN4 I O connector for PMC Site 2 These li...

Page 34: ...led high Ground Ground 12 VDC 7 PETp6B PETn6B 3 3 VDC PETp7B PETn7B 5 VDC 8 Ground Ground TDI pulled high Ground Ground 12 VDC 9 No Connect No Connect No Connect No Connect No Connect 5 VDC 10 Ground Ground No Connect Ground Ground Ground 11 PERp0B PERn0B No Connect PERp1B PERn1B 5 VDC 12 Ground Ground Ground Ground Ground No Connect 13 PERp2B PERn2B 3 3 VDC PERp3B PERn3B 5 VDC 14 Ground Ground Gr...

Page 35: ...connect a dumb terminal or a PC running a terminal emulation utility like Hyperterminal to COM1 via a null modem Next set the communications parameters of the host s terminal program to 115Kbaud Other parameters are 8 bit no parity and one stop bit Do not enable XON XOFF or hardware flow control With this link set up power on the system Press C a few times on your dumb terminal or your PC as the s...

Page 36: ...he menu to the right of the currently displayed menu in the menu bar PGUP key Move the cursor up several lines a full window s worth scrolling the window as necessary PGDN key Move the cursor down several lines a full window s worth scrolling the window as necessary HOME key Move the cursor to the first configurable field in the current menu scrolling the window as necessary END key Move the curso...

Page 37: ...lf this information is useful when obtaining support for your system PLEASE CALL Dynatem at 800 543 2830 FOR BIOS SUPPORT DO NOT CALL GENERAL SOFTWARE DIRECTLY BIOS Version Indicates the major and minor core architecture versions 6 x where x is a number from 0 to 999 BIOS Build Date Date in MM DD YY format on which Dynatem built the system BIOS binary file System BIOS Size Size of BIOS exposed in ...

Page 38: ...rs are normally specified in military time thus 13 means 1pm or one hour after noon whereas 01 means 1am or one hour after midnight When the cursor leaves RTC fields they either affect the battery backed RTC right away allowing the system to continue with your new settings or they revert back to old values if the new values are not valid entries B 5 Exit Setup Menu The Exit menu provides methods f...

Page 39: ...n the list become candidates for booting the OS The BBS list also contains other boot actions such as boot from network cards and PCI slots as well as special BIOS boot actions like Boot EFI Boot Windows CE or even Boot Debugger When deciding what boot action to do first and then next in succession POST first scans all the drives in the list to verify they are present and operating properly as des...

Page 40: ...ant on functionality even when the OS is not available or is still loading The photograph above shows a common setup of the BBS list for desktop applications In this example the first boot device is theWestern Digital IDE hard drive WDC WD800JB 00JJC0 connected to the target as a Primary Master IDE drive The second boot device is the Secondary Master and this is the on board CompactFlash The third...

Page 41: ... configure POST This menu is shown in the following figure scrolled down more so the full set of options can be seen Be sure to review the Features menu where additional items can be configured such as the Splash Screen and BIOS initiatives The figure below shows the same menu scrolled down so that the remainder of its fields may be viewed ...

Page 42: ...if POST is configured to ask interactive questions of the user about whether to load specific features i e whether or not to load SMM POST Display PCI Devices Enable display of PCI devices POST Display PnP Devices Enable display of ISA PnP devices The following table describes the settings associated with the POST setup menu s Debugging section POST Debugger Breakpoints Enable processing of INT 3 ...

Page 43: ...to support legacy OSes like DOS Windows95 Windows98 and WindowsNT Disable for operating systems like WindowsXP or Windows Vista or for Linux operating systems with ACPI support Plug n Play OS Enable delay of configuration of PnP hardware and option ROMs When enabled BIOS will NOT configure the devices and instead defer assignment of resources such as DMA I O memory and IRQs to the PnP OS When disa...

Page 44: ...orts COM3 COM4 Basically this window is used to configure COM3 COM4 though they are referred to as Serial Ports 1 2 in the SIO Setup Menu POST reads these settings in the menu shown above and programs the Super I O part accordingly enabling and disabling devices as requested The disabled devices are not further programmed since they are actually disabled in hardware In the figure above legacy I O ...

Page 45: ...ACPI replaces PnP and APM Used with ACPI aware OSes such as Linux kernels version 2 6 and above Windows XP and Windows Vista Commonly also uses the SMM feature see Firmbase to operate properly POST Memory Manager PMM Enable memory allocation services for option ROMs especially network cards running PXE Some option ROMs may use this interface incorrectly causing system crashes Other PXE option ROMs...

Page 46: ...e menu configures the Firmbase Technology component of the system BIOS including all of the features enabled by it i e legacy USB keyboard and mouse boot from USB devices and support of Firmbase applications such as Boot Security Platform Update Facility and High Availability Monitor This menu has several parts with the most basic user oriented feature options in the top section and the more techn...

Page 47: ...rmbase Technology to operate Firmbase Debug Log Specifies the device used by Firmbase Technology components kernel drivers and programs to display debugging instrumentation produced with the dprintf and DPRINTF system functions None Instrumentation disabled COM1 Write text to 1st serial port COM2 Write text to 2nd serial port COM3 Write text to 3rd serial port COM4 Write text to 4th serial port Vi...

Page 48: ... all possible with the consequence that the program may not operate correctly B 12 Miscellaneous Setup Menu The Misc menu provides for configuration of BIOS settings that don t easily fit in any other category They include Cache Control Keyboard Control Debugger Settings and System Monitor Utility Configuration parameters The following table presents the settings in the Misc Setup menu System Cach...

Page 49: ...ard Disk Write Stimulation Enables System Monitor s write of a preconfigured number of sectors to a location on the first hard disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first hard drive is configured in the BBS list as a USB hard drive Please note that when this parameter is selected the system automatically en...

Page 50: ...Appendix B BIOS Setup 46 CPU 71 10 XPD RPD DPD VMEbus Core 2 Duo Processor Board User s Manual ...

Page 51: ...z Core Duo 5 VDC 6 0 A typ 3 0 VDC Lithium Coin Cell 3 4 A Power Requirements The 3 Volt lithium coin cell is a CR2032 with 190 mAhours capacity and it is used to battery back the Real Time Clock the 2 MB of NV SRAM and the BIOS s NV RAM At 3 4 A this battery should last for over six years with power off Condition Environmental Requirements Operating Temperature 20 to 85 C with Thermal Monitor II ...

Page 52: ...Appendix C Power Environment Requirements 48 CPU 71 10 XPD RPD DPD VMEbus Core 2 Duo Processor Board User s Manual ...

Page 53: ... and keyboard ports are routed through P2 The two Ethernet ports two SATA ports and the VGA port are routed through P0 Two Serial ATA ports are routed through RP0 The XPDPTB also routes two VITA 31 1 compliant 1 Gb Ethernet ports from RP0 to two industry standard connectors for situations where VITA 31 1 backplane fabric switching is not used The Super I O device used for COM3 4 P S2 Mouse Keyboar...

Page 54: ...33 DA1 34 No connection 35 DA0 36 DA2 37 CS1Fx 38 CS3Fx 39 LED Control 40 GND Primary IDE Interface Connector J5 40 pin Dual row 0 1 Header COM1 and COM2 ports are set up for RS 232 operation J3 is used for COM1 and J4 is used for COM2 The pinouts of the two connectors are identical Pin RS 232 Signals 1 Data Carrier Detect DCD Input 2 Received Data RxD Input 3 Transmitted Data TxD Output 4 Data Te...

Page 55: ...OM3 J2 and COM4 J1 Connectors DB9M Connector The metal shell of the connector goes to chassis ground J9 SATA1 and J10 SATA0 are Serial ATA connectors where both ports have the following pinout Pin Signal 1 GND 2 A 3 A 4 GND 5 B 6 B 7 GND Serial ATA Connectors J9 J10 Pinout for either of the connectors J12 combines the PS 2 Mouse and Keyboard interfaces on one connector A Y splitter cable is requir...

Page 56: ...100 Signal Description Gb Signal Description A1 Port A Transmit Data TX TP0 A2 A Transmit Data TX TP0 A3 A Receive Data RX TP1 A4 Unused TP2 A5 Unused TP2 A6 A Receive Data RX TP1 A7 Unused TP3 A8 Unused TP3 J6 Pin 10 100 Signal Description Gb Signal Description B1 Port B Transmit Data TX TP0 B2 B Transmit Data TX TP0 B3 B Receive Data RX TP1 B4 Unused TP2 B5 Unused TP2 B6 B Receive Data RX TP1 B7...

Page 57: ...xpansion Module for the XPD CPU 71 10 XPD RPD DPD VMEbus Core 2 Duo Processor Board User s Manual 53 DYNATEM Toll free 1 800 543 3830 Tel 1 949 855 3235 Fax 1 949 770 3481 Email sales dynatem com Email tech dynatem com Web www dynatem com ...

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