[/0
channel description
The
following
is
a
description
of
the PC/XT
l/O
channel.
All
lines
are
TTL
compatible.
OSC,
oscillator
It
is
a high-speed
clock
with
a
70ns
period
(14.31818MHz).
It
has a
50% duty cycle.
CLK,
system clock
It
operates at
one-third
the frequency
of
the
oscillator
and
has a
period
of
210ns
(4.77MHz). The
clock.
has a
33%
duty cycle.
Reset
This
line is
used
to
reset
or initialize
system
logic upon
power up or during
a
low line
voltage
outage.
This signal
is
synchronized
to
the
falling
edge
of
the
clock
and
is
active
high.
AO-A 19,
address
bits
0
to
19
These
lines
are used
to
address
memory and
l/O
devices
within
the system.
The 20
address
lines allow
access
of
up to
1
megabyte
of
memory.
A0 is
the least
significant
bit
(LSB)
while A19
is
the
most significant
bit
(MSB).
These
lines
are generated
by
either the processor
or
the
DMA
controller. They
are
active
high.
DO-D7,
data bits
0
to
7
These
lines provide
data bus
bits
0
to
7 for
the processor,
memory
and
l/O
devices.
D0 is
the least
significant
bit
(LSB)
while
D7 is
the
most significant
bit (MSB).
These
lines
are
active
high.
26
)
0
O
ALE,
address
latch enable
This line is
used
on
the system board
to latch valid
addresses
from
the processor.
it
is
available
to
the
l/O
channel
as
an
indicator
of
a
valid
processor address
(when
used
with AEN).
Processor
addresses
are latched
with
the
falling
edge
of ALE.
[/0
CH
CK,
[/0 channel check
This line
provides the
processor
with
parity
(error)
information on memory or
devices
in
the
l/O
channel.
When this signal
is
active
low,
a
parity error
is
activated.
[/0
CH
RDY,
I/O
channel ready
This line, normally
high
(ready),
can
be pulled
low
(not
ready)
by
a
memory or an
l/O
device
to
lengthen
l/O
or
memory cycles.
It
allows slower
devices
to
attach
to
the
l/O
channel
with
a
minimum
of difficulty. Any
slow
device
using this
line
should
drive
it
low
immediately upon
detecting
a
valid
address
and a
real or write
command.
This
line
should
never
be held
low
more
than
10
clock
cycles. Machine
cycles
(I/O
or memory)
are extended
by
an integral number
of CLK
cycles.
[3024307,
interrupt
requests
2
to
7
These
lines
are used
to signal
the processor that
an
I/O
device requires
attention. They
are
prioritized
with IRQZ
having
the
highest
priority
and
IRQ7
having
the
lowest.
An
interrupt
request
is
generated
by
raising an lRQ
line (low
to
high)
and
holding
it
high until
it
is
acknowledged
by
the
processor
(interrupt
service
routine).
103,
[/0
read
command
This
command
line
instructs an
|/O
device to drive
its
data
onto
the data
bus.
It
may be driven
by
the processor
orthe
DMA
controller. This signal
is
active
low.
27
