BIOS Setup Information
96M4281o User’s Manual
4-12
4.8
Advanced Chipset Feature
This section allows you to configure the system based on the specific features of the
Intel 945GM chipset. This chipset manages bus speeds and access to system
memory resources, such as DRAM (DDR II SO-SDRAM) and the external cache. It
also coordinates communications between the conventional PCI Express bus and PCI
bus. It must be stated that these items should never need to be altered. The default
settings have been chosen because they provide the best operating conditions for
your system. The only time you might consider making any changes would be if you
discovered that data was being lost while using your system.
Phoenix- AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable
[By SPD]
X CAS Latency Time
Auto
X DRAM RAS# to CAS# Delay
Auto
X DRAM RAS# Precharge
Auto
X Precharge delay (tRAS)
Auto
X System Memory Frequency
Auto
SLP_S4# Assertion Width
[1 to 2 Sec.]
System BIOS Cacheable
[Enabled]
Video BIOS Cacheable
[Disabled]
Memory Hole At 15M-16M
[Disabled]
f
PCI Express Root Port Func [Press Enter]
** VGA Setting **
PEG/Onchip VGA Control
[Auto]
On-Chip Frame Buffer Size
[ 8MB]
DVMT Mode
[DVMT]
DVMT /FIXED Memory Size [ 128MB]
Boot Display
[Auto]
Panel Scaling
[Auto]
Panel Number
[640X480 18bit 1ch]
Menu Level
f
↑↓→←
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable
This option provides DIMM plug-and-play support by serial presence detect (SPD)
mechanism via the system management bus (SMBUS) interface.
The choice: Manual, By SPD.