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Document Number DS39931 Rev 2-2

 

 

 

 

 

 

 

 

 

 

 

 

 

PI7C9X2G304EL 

PCI EXPRESS GEN 2 PACKET SWITCH 

3-Port, 4-Lane, ExtremeLo PCIe2.0 Packet Switch

 

DATASHEET

 

REVISION 2-2 

September 2017

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1545 Barber  Lane  Milpitas, CA 95035 

Telephone:  408-232-9100 

FAX:  408-434-1040 

Internet: 

http://www.diodes.com

 

 

Summary of Contents for PI7C9X2G304EL

Page 1: ...I7C9X2G304EL PCI EXPRESS GEN 2 PACKET SWITCH 3 Port 4 Lane ExtremeLo PCIe2 0 Packet Switch DATASHEET REVISION 2 2 September 2017 1545 Barber Lane Milpitas CA 95035 Telephone 408 232 9100 FAX 408 434 1...

Page 2: ...United States international or foreign patents pending Product names and markings noted herein may also be covered by one or more United States international or foreign trademarks This document is w r...

Page 3: ...le 9 2 JTAG Device ID Register Updated Table 9 3 JTAG Boundary Scan Register Definition Updated Table 11 2 DC Electrical Characteristics 09 11 15 1 3 Updated Table 11 1 AbsoluteMaximum Ratings 12 23 1...

Page 4: ...ND DE EMPHASIS SETTINGS 19 5 1 6 DRIVE AMPLITUDE 20 5 1 7 DRIVE DE EMPHASIS 21 5 1 8 TRANSMITTER ELECTRICAL IDLE LATENCY 21 5 2 DATA LINK LAYER DLL 21 5 3 TRANSACTION LAYER RECEIVE BLOCK TLP DECAPSULA...

Page 5: ...ISTER OFFSET 30h 44 7 2 25 CAPABILITY POINTER REGISTER OFFSET 34h 45 7 2 26 INTERRUPT LINE REGISTER OFFSET 3Ch 45 7 2 27 INTERRUPT PIN REGISTER OFFSET 3Ch 45 7 2 28 BRIDGE CONTROL REGISTER OFFSET 3Ch...

Page 6: ...LOT CONTORL REGISTER 2 OFFSET F8h 67 7 2 83 SLOT STATUS REGISTER 2 OFFSET F8h 67 7 2 84 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER OFFSET 100h 67 7 2 85 UNCORRECTABLE ERROR STATUS REGIST...

Page 7: ...OP LATENCY REGISTER OFFSET 234h Upstream Port Only 79 8 CLOCKSCHEME 80 9 IEEE 1149 1 COMPATIBLE JTAG CONTROLLER 81 9 1 INSTRUCTION REGISTER 81 9 2 BYPASS REGISTER 81 9 3 DEVICE ID REGISTER 81 9 4 BOUN...

Page 8: ...PHASIS BASE LEVEL SETTINGS 21 TABLE 5 9 SUMMARY OF PCI EXPRESS ORDERING RULES 24 TABLE 6 1 SMBUS ADDRESS PIN CONFIGURATION 36 TABLE 7 1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION 75 TABLE 7 2 TABLE ENTR...

Page 9: ...ed Power Saving Empty downstreamports are set to idle state to minimize power consumption Link Power Management Supports L0 L0s L1 L2 L2 L3Ready and L3 link power states Active state power management...

Page 10: ...ccept them As to the packets required to follow the ordering rule the Head Of Line HOL issue becomes unavoidable for packets destined to different egress ports since the operation of producer consumer...

Page 11: ...ntegrated Reference Clock Buffer of the PCI Express Switch supports three reference clock outputs The clock buffer is from a single 100MHz clock input and distributes the clock source to three outputs...

Page 12: ...states of wholechipexcept stickylogics are initialized Please refer toTable 11 2forPERST_L spec DWNRST_L 2 1 K2 G1 O Downstream Device Reset Active LOW DWNRST_Lprovides a reset signal to the devices c...

Page 13: ...wn resistor be used PRSNT 2 1 AA1 Y2 I Present WhenPRSNT is assertedlow it indicates that the device is present in theslot ofdownstreamport Otherwise it indicates the absence of the device PRSNT x is...

Page 14: ...pulledlowwhen system is reset the Power Saving Mode is disabled When this pinis pulledlow it shouldbe tiedto groundthrough a 330 ohm pull down resistor Whenthis pin is pulled high a 5 1K ohmpull up re...

Page 15: ...in conjunction with TCK to shift data andinstructions intothe TAP in a serial bit stream WhenJTAGboundary scan functionis not implemented this pin shouldbe left open NC TRST_L H34 I Test Reset Active...

Page 16: ...KI_N AR5 GPIO 1 A27 PERN 2 J1 NC AG1 SMBCLK AR7 GPIO 2 A29 PETN 1 J35 TCK AG35 REFCLKI_P AR9 GPIO 4 A31 PETP 1 K2 DWNRST_L 2 AH2 PWR_SAV AR11 GPIO 5 A33 NC K34 TMS AH34 EEPD AR13 GPIO 7 A35 NC L1 TEST...

Page 17: ...framer 8B 10B encoder decoder receiver elastic buffer and PIPE PHY control status circuitries To provide the flexibility for port configuration each lane has its own control and status signals for MAC...

Page 18: ...R SWING The PCI Express transmitters support implementations of both full voltage swing and half low voltage swing In full swing signaling mode the transmitters implement de emphasis while in half swi...

Page 19: ...set 74h bit 20 16 bit 25 21 and bit 30 26 listed in Table 5 5 is active depending on the de emphasis and swing condition The settings and the corresponding values of the amplitude level are listed in...

Page 20: ...112 5 11101 181 0 01000 50 0 10011 119 0 11110 187 5 01001 56 0 10100 125 0 11111 194 0 01010 62 5 10101 131 0 Note 1 Nominal levels Actual levels will vary withtemperature voltage andboardeffects 2...

Page 21: ...s reported as an error associated with the receiving port To ensure end to end data integrity a 32 bit ECRC is checked against the TLP at the receiver if the digest bit is set in header 5 4 ROUTING Th...

Page 22: ...ng posted request data If the received TLP is of the posted request type and is determined to have payload coming with the header the payload data would be put into PD queue There are two PD queues fo...

Page 23: ...When the Relaxed Ordering Attribute bit is cleared a Read completion must pull ahead of previously queued posted data transmitting in the same direction In this case the read data transmits in the sa...

Page 24: ...its from the opposite end in a link The output port broadcasts themto all the otheringress ports to get packet transmission 5 11 TRANSATION LAYER TRANSMIT BLOCK TLP ENCAPSULATION The transmit portion...

Page 25: ...6 1 2 EEPROM MODE AT RESET During a reset the Switch will automatically load the information data from the EEPROM if the automatic load condition is met The first offset in the EEPROM contains a sign...

Page 26: ...6h Reserved 48h Reserved 4Ah Reserved 4Ch Reserved 4Eh PM Data for Port 0 PM Capability for Port 0 50h PM Data for Port 1 PM Capability for Port 1 52h PM Data for Port 2 PM Capability for Port 2 54h R...

Page 27: ...ed BEh XPIP_CSR3 16 31 for Port 0 C0h XPIP_CSR3 16 31 for Port 1 C2h XPIP_CSR3 16 31 for Port 2 C4h Reserved C6h Reserved C8h Reserved CAh Reserved CCh Reserved CEh REV_TS_CTR Replay Time out Counter...

Page 28: ...t 0 2 74h Bit 15 70h Port 0 2 70h Bit 13 8Ch Port0 2 8Ch Bit 5 CCh Port 1 2 CCh Bit 21 8Ch Port0 2 8Ch Bit 6 8Ch Port0 2 8Ch Bit 0 CCh Port 0 2 CCh Bit 19 8Ch Port0 2 8Ch Bit 1 E4h Port 0 2 E4h Bit 12...

Page 29: ...11 7 C_EMP_POST_HALF_DELTA XPIP_CSR6 4 1 for Port0 2 Bit 15 12 XPIP_CSR6 4 1 16h 84h Port 0 2 84h Bit 15 0 XPIP_CSR4 15 0 for Port 0 2 Bit 15 0 XPIP_CSR4 15 0 18h 84h Port 0 2 84h Bit 31 16 XPIP_CSR4...

Page 30: ...13 Change Speedselect Change_Speed_En forPort2 Bit 15 Change Speedenable 30h 7Ch Port0 7Ch Bit 30 16 PHY Parameter2_1 for Port 0 Bit 14 0 PHY parameter2 32h 7Ch Port1 7Ch Bit 30 16 PHY Parameter2_1 f...

Page 31: ...1 AUX Current Bit 4 readonly as 1 toindicate Bridge supports the D1 power management state Bit 5 readonly as 1 toindicate Bridge supports the D2 power management state Bit 7 6 PMESupport for D2andD1 s...

Page 32: ...henset the component uses the clock providedon the Connector Device specific Initialization forPort2 Bit 2 Whenset the DSI is required LPVC CountforPort2 Bit 3 Whenset the VC1 is allocatedtoLPVC of Eg...

Page 33: ...4h D4h Port2 D4h Bit 31 16 Slot Capability1 of Port 2 Bit 15 0 Mappingtothe highwordof slot capabilityregister B0h 80h Port 0 80h Bit 15 0 XPIP_CSR3_0 for Port 0 Bit 15 0 XPIP_CSR3 15 0 B2h 80h Port 1...

Page 34: ...5 8 Whenset it indicates the correspondingTC is mapped into VC1 F2h 15Ch Port 1 15Ch Bit 22 16 160h Port1 160h Bit 7 0 VC1 MAXTime Slot and TC VC Map for Port 1 Bit 6 0 The maximum timeslot supportedb...

Page 35: ...s that can be auto loaded by the EEPROM interface can also be read and written by the SMBus interface This feature allows increases in the system expandability and flexibility in systemimplementation...

Page 36: ...Number Secondary Bus Number Primary Bus Number 18h Secondary Status I O Limit Address I O Base Address 1Ch Memory Limit Address Memory Base Address 20h Prefetchable Memory Limit Address Prefetchable M...

Page 37: ...he first extended capability always begins at offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at an offset greater than 0FFh relative to the beginnin...

Page 38: ...OFFSET 00h BIT FUNCTION TYPE DESCRIPTION 31 16 Device ID RO Identifies this device as the PI7C9X2G303EL The default value maybe changedby SMBus or auto loadingfromEEPROM Resets to 2304h 7 2 3 COMMAND...

Page 39: ...Switch port is not reflectedin this bit Must be hardwiredto 0b 20 Capabilities List RO Set to 1 to enable support for the capabilitylist offset 34his the pointer to the data structure Reset to 1b 21 6...

Page 40: ...fieldis implementedby PCI Express devices as a RW fieldfor legacy compatibility but it has noimpact on any PCI Express device functionality Reset to 00h 7 2 8 PRIMARY LATENCY TIMER REGISTER OFFSET 0C...

Page 41: ...s address register Reset to 0h 7 2 15 I O LIMIT ADDRESS REGISTER OFFSET 1Ch BIT FUNCTION TYPE DESCRIPTION 11 8 32 bit Indicator RO Read as 01h to indicate 32 bit I O addressing 15 12 I O Limit Address...

Page 42: ...ine when to forwardmemory transactions fromone interface tothe other The upper 12 bits correspondto address bits 31 20 andare able to be writtento The lower 20 bits correspondingto address bits 19 0 a...

Page 43: ...ange for the Bridge to determine when to forwardmemory readandwrite transactions from one interface to theother Reset to 0000_0000h 7 2 22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32 BITS REGISTER OFFS...

Page 44: ...dary interface Reset to 0b 17 S_SERR enable RW 0b Disables the forwardingofEER_COR ERR_NONFATALand ERR_FATALfromsecondary to primaryinterface 1b Enables the forwardingofEER_COR ERR_NONFATALand ERR_FAT...

Page 45: ...nagement Revision RO Read as 011bto indicate the device is compliant toRevision1 2ofPCI Power Management InterfaceSpecifications 19 PME Clock RO Does not apply to PCI Express Must be hardwiredto0b 20...

Page 46: ...T RO Does not apply to PCI Express Must be hardwiredto0b 23 Bus Power Clock Control Enable RO Does not apply to PCI Express Must be hardwiredto0b 7 2 32 DATA REGISTER OFFSET 44h BIT FUNCTION TYPE DESC...

Page 47: ...tream Port Only BIT FUNCTION TYPE DESCRIPTION 31 0 Message Upper Address RW This register is onlyeffective if the devicesupports a 64 bit message address is set Reset to 0000_0000h 7 2 37 MESSAGE DATA...

Page 48: ...CAPABILITY REGISTER OFFSET 64h BIT FUNCTION TYPE DESCRIPTION 7 0 Enhanced Capabilities ID RO Read as 09h to indicate that these are vendor specific capabilityregisters 15 8 Next ItemPointer RO Pointer...

Page 49: ...is workingunder cut through mode The default value maybe changedby SMBus or auto loadingfrom EEPROM Reset to 0b 2 1 Cut through Threshold RW Cut through Threshold Whenforwardinga packet fromlow speed...

Page 50: ...edby SMBus or auto loadingfrom EEPROM Reset to 1_0011b 25 21 C_DRV_LVL_6P0_ NOM RO The default value may be changedby SMBus or auto loadingfrom EEPROM Reset to 1_0011b 30 26 C_DRV_LVL_HALF _NOM RO The...

Page 51: ...efault value may be changedby SMBus or auto loadingfrom EEPROM Reset to 1_1101b 31 Reserved RsvdP Not Support 7 2 50 PHY PARAMETER 2 OFFSET 7Ch BIT FUNCTION TYPE DESCRIPTION 3 0 C_TX_PHY_ LATENCY RO T...

Page 52: ...2 RO The default value may be changedby SMBus or auto loadingfrom EEPROM Reset to 1000b 30 P_TXSWING RO The default value may be changedby SMBus or auto loadingfrom EEPROM Reset to 0b 31 Reserved Rsvd...

Page 53: ...PROM Reset to 1b 5 MW Overpass Disable RW The default value may be changedby SMBus or auto loadingfrom EEPROM Reset to 0b 6 OrderingFrozen Disable RW Disable the RO orderingrule The default value may...

Page 54: ...Multilane RXEQ RO Upstreamp Port only Reset to 86h Reservedfor DownstreamPort Reset to00h 31 24 Reserved RsvdP Not Support 7 2 57 OPERATION MODE OFFSET 98h BIT FUNCTION TYPE DESCRIPTION 15 0 Operation...

Page 55: ...O State of GPIO 0 pin 1 GPIO 0 Output Enable RW 0b GPIO 0 is an input pin 1b GPIO 0 is an output pin Reset to 0b 2 GPIO 0 Output Register RW Value of this bit will be output toGPIO 0 pinif GPIO 0 is c...

Page 56: ...f GPIO 5 is configuredas an output pin Reset to 0b 23 Reserved RsvdP Not Support 24 GPIO 6 Input RO State of GPIO 6 pin 25 GPIO 6 Output Enable RW 0b GPIO 6 is an input pin 1b GPIO 6 is an output pin...

Page 57: ...PTION 8 Reserved RsvdP Not Support 15 9 EEPROM Address RW Contains the EEPROM address Reset to 0000h 7 2 64 EEPROM DATA REGISTER OFFSET BCh Upstream Port Only BIT FUNCTION TYPE DESCRIPTION 31 16 EEPRO...

Page 58: ...ansition from L0s state to theL0 state ForSwitch the ASPM software wouldnot check this value Reset to 000b 11 9 Endpoint L1 Acceptable Latency RO Acceptable total latencythat an Endpoint can withstand...

Page 59: ...ead Reset to 0b 9 PhantomFunction Enable RW Does not apply to PCI Express Switch Returns 0 when read Reset to 0b 10 Auxiliary AUX Power PM Enable RWS When set indicates that a device is enabledtodrawA...

Page 60: ...supports L0s andL1 entry Thedefault value maybe changedby SMBus or auto loadingfrom EEPROM Reset to 00b 14 12 L0s Exit Latency RO Indicates the L0s exit latencyforthe givenPCIeLink The lengthoftime th...

Page 61: ...This bit always returns 0bwhen read 6 Common Clock Configuration RW 0b The components at bothends of a link areoperatingwith asynchronous reference clock 1b The components at bothends of a link areope...

Page 62: ...r this slot The default value may be changedby SMBus or auto loading from EEPROM Reset to 0b 1 Power Controller Present RO When set it indicates that a Power Controlleris implementedfor this slot The...

Page 63: ...it enables the generationof Hot Pluginterrupt or wakeup event on a power fault event Reset to 0b 2 Reserved RsvdP Not Support 3 Presence Detect ChangedEnable RW When set it enables the generationof H...

Page 64: ...tes an issuedcommand Reset to 0b 21 MRL Sensor State RO Reflects the status of MRL Sensor 0b MRL Closed 1b MRL Opened Reset to 0b 22 Presence Detect State HwInt RO Indicates the presence of a cardin t...

Page 65: ...ION 31 16 Device status 2 RO Reset to 0000h 7 2 78 LINK CAPABILITIES REGISTER 2 OFFSET ECh BIT FUNCTION TYPE DESCRIPTION 31 0 Link Capabilities 2 RO Reset to 0000_0000h 7 2 79 LINK CONTROL REGISTER 2...

Page 66: ...apability Offset RO Pointer points to thePCI Express ExtendedVC capabilityregister Reset to 140h 7 2 85 UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h BIT FUNCTION TYPE DESCRIPTION 0 TrainingError St...

Page 67: ...svdP Not Support 12 PoisonedTLP Mask RWS When set anevent of PoisonedTLP has been receivedor generatedis not logged in the Header Logregister andnot issuedas an Error Message toRC either Reset to 0b 1...

Page 68: ...rror Severity RWS 0b Non Fatal 1b Fatal Reset to 1b 11 5 Reserved RsvdP Not Support 12 PoisonedTLP Severity RWS 0b Non Fatal 1b Fatal Reset to 0b 13 Flow Control Protocol Error Severity RWS 0b Non Fat...

Page 69: ...SET 114 h BIT FUNCTION TYPE DESCRIPTION 0 Receiver ErrorMask RWS When set theReceiver Errorevent is not loggedin theHeader Logregister andnot issuedas an Error Message to RC either Reset to 0b 5 1 Res...

Page 70: ...the 3rdDWORD ofTLP Header The Headbyte is in bigendian 127 96 4th DWORD ROS Holdthe 4thDWORDof TLP Header The Headbyte is in bigendian 7 2 92 PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER OFFSET 140...

Page 71: ...31 24 VC Arbitration Table Offset RO It indicates the locationofthe VC Arbitration Table as an offset fromthe base address of the Virtual Channel Capability registerin the unit of DQWD 16 bytes Reset...

Page 72: ...s the locationofthe Port Arbitration Table n as an offset fromthe base address of the Virtual Channel Capabilityregister in the unit ofDQWD 16 bytes Reset to 04hforPort ArbitrationTable 0 7 2 98 VC RE...

Page 73: ...bit 0 1 Reset to 00hif offset 144h bit 0 0 13 8 Reserved RsvdP Not Support 14 AdvancedPacket Switching RO When set it indicates the VC resource only supports transactionoptimizedfor AdvancedPacket Swi...

Page 74: ...le Status RO When set it indicates that any entryof thePort ArbitrationTable is written by software This bit is clearedwhen hardware finishes loadingvalues storedin the Port ArbitrationTable afterthe...

Page 75: ...ase 49 48 18h Phase 79 78 Phase 77 76 Phase 75 74 Phase 73 72 Phase 71 70 Phase 69 68 Phase 67 66 Phase 65 64 20h Phase 95 94 Phase 93 92 Phase 91 90 Phase 89 88 Phase 87 86 Phase 85 84 Phase 83 82 Ph...

Page 76: ...20 18 Power Rail RO It specifies the power rail of the givenoperationcondition Reset to 010b 31 21 Reserved RsvdP Not Support 7 2 108 POWER BUDGET CAPABILITY REGISTER OFFSET 218h BIT FUNCTION TYPE DE...

Page 77: ...le RW Enable ACS TranslationBlocking Reset to 0b 18 ACS P2P Request Redirect RW Enable ACS P2P Request Redirect Reset to 0b 19 ACS P2P CompletionRedirect Enable RW Enable ACS P2P CompletionRedirect Re...

Page 78: ...torequest Reset to 000h 12 10 Max Snoop Latency Scale RW This register provides a scale for thevalue containedwithinthe Maximum Snoop LatencyValue field Reset to 000b 15 13 Reserved RsvdP Not Support...

Page 79: ...g table When CLKBUF_PD pin is asserted high the clock buffer is in power down mode and disabled The 100MHz Reference Clock Output Pairs are disabled and The PI7C9X2G304EL requires 100MHz differential...

Page 80: ...tion Register Codes Instruction Operation Code binary Register Selected Operation EXTEST 00000 Boundary Scan Drives receives off chip test data SAMPLE 00001 Boundary Scan Samples inputs pre loads outp...

Page 81: ...akes place on the rising edge of TCK 9 5 JTAG BOUNDARY SCAN REGISTER ORDER Table 9 3 JTAG Boundary Scan Register Definition Boundary Scan Register Number Pin Name Ball Location Type Tri state Control...

Page 82: ...com Diodes Incorporated PI7C9X2G304EL Boundary Scan Register Number Pin Name Ball Location Type Tri state Control Cell 43 Internal 44 Internal 45 Control 46 Internal 47 CLKBUF_PD AP28 Birdir 45 48 Int...

Page 83: ...ates During the transition from D3 hot to D3 cold state the main power supplies of VDDC and VDDR are turned off to save power while keeping the VDDCAUX and VAUX with the auxiliary power supplies to ma...

Page 84: ...during this stabilization time the REFCLK starts and stabilizes After there has been time 100 ms for the power and clock to become stable PERST is deasserted high and the PCI Express functions can st...

Page 85: ...orextendedperiods of time may affect reliability 12 2 DC SPECIFICATIONS Table 12 2 DC Electrical Characteristics Symbol Description Min Typ Max Unit VDDC1 Digital Core Power 0 95 1 0 1 1 V VDDR Digita...

Page 86: ...to Lane Output Skew LTX SKEW 500 ps 4 UI ps Table 12 4 PCI Express Interface Differential Transmitter TX Output 2 5 Gbps Characteristics Parameter Symbol Min Typ Max Unit Unit Interval UI 399 88 400 0...

Page 87: ...p 65 175 mV Lane to Laneskew LRX SKEW 20 ns 12 4 OPERATING AMBIENT TEMPERATURE Table 12 7 Operating Ambient Temperature Above which the useful life may be impaired Item Min Max Units Ambient Temperat...

Page 88: ...DS39931 Rev 2 2 www diodes com Diodes Incorporated PI7C9X2G304EL 13 PACKAGE INFORMATION The package of PI7C9X2G304EL is a 10mm x 10mm aQFN 136 Pin package The following are the package information an...

Page 89: ...PI7C9X2G304EL Page 90 of 90 September 2017 Document Number DS39931 Rev 2 2 www diodes com Diodes Incorporated PI7C9X2G304EL Figure 13 2 Package bottom view...

Page 90: ...ed PI7C9X2G304EL 14 ORDERING INFORMATION Part Number Temperature Range Package Pb Free Green PI7C9X2G304EL ZXAEX 40o to 85o C Industrial Temperature 136 pin aQFN 10mm x 10mm Yes PI 7C 9X2G304EL ZXA E...

Page 91: ...tronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Diodes Incorporated PI7C9X2G304ELZXAE PI7C9X2G304ELZXAEX PI7C9X2G304ELQZXAEX PI7C9X2G304ELQZXAE PI7C9X2G30...

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