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J1
– HDMI connector: JST SM20B-SRDS (Matching type : JST SHDR-20V-S-B)
PIN
SYMBOL
DESCRIPTION
1
GND
Ground
2
GND
Ground
3
RXC+
TMDS Data C+
4
RXC-
TMDS Data C-
5
RX0+
TMDS Data 0+
6
RX0-
TMDS Data 0-
7
RX1+
TMDS Data 1+
8
RX1-
TMDS Data 1-
9
RX2+
TMDS Data 2+
10
RX2-
TMDS Data 2-
11
GND
Ground
12
GND
Ground
13
MSTR2_SCL
Reserved
14
MSTR2_SDA
Reserved
15
DDC_5V
+5V power supply for DDC (optional)
16
HPD
Hot plug detection
17
DDC_SCL
DDC serial clock
18
DDC_SDA
DDC Data
19
VCC1
VCC 5V output
20
VCC2
VCC 5V output
J3
– LVDS output connector: JAE FI-RE51S-HF (Matching type : JAE FI-RE51HL)
PIN
SYMBOL
DESCRIPTION
1
VDD (+12V)
Panel power supply (+12V) (selected by JA3)
2
VDD (+12V)
Panel power supply (+12V) (selected by JA3)
3
VDD (+12V)
Panel power supply (+12V) (selected by JA3)
4
VDD (+12V)
Panel power supply (+12V) (selected by JA3)
5
VDD (+12V)
Panel power supply (+12V) (selected by JA3)
6
VDD (3,3V/5V)
Panel power supply (3,3V/5V) (selected by JA3)
7
VDD (3,3V/5V)
Panel power supply (3,3V/5V) (selected by JA3)
8
VDD (3,3V/5V)
Panel power supply (3,3V/5V) (selected by JA3)
9
VDD (3,3V/5V)
Panel power supply (3,3V/5V) (selected by JA3)
10
VDD (3,3V/5V)
Panel power supply (3,3V/5V) (selected by JA3)
11
GND
Ground
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
GND
Ground
16
NC
No connection
17
NC
No connection
18
NC
No connection
19
NC
No connection
20
GND
Ground
21
GND
Ground
22
NC
No connection
23
NC
No connection
24
TXA3+
Positive differential LVDS data bit A3
25
TXA3-
Negative differential LVDS data bit A3
26
GND
Ground
27
TXAC+
Positive LVDS clock for A channel
28
TXAC-
Negative LVDS clock for A channel
29
GND
Ground
30
TXA2+
Positive differential LVDS data bit A2
31
TXA2-
Negative differential LVDS data bit A2
32
TXA1+
Positive differential LVDS data bit A1
33
TXA1-
Negative differential LVDS data bit A1
34
TXA0+
Positive differential LVDS data bit A0
35
TXA0-
Negative differential LVDS data bit A0
36
GND
Ground
37
NC
No connection
38
NC
No connection
39
TXB3+
Positive differential LVDS data bit B3
40
TXB3-
Negative differential LVDS data bit B3
41
GND
Ground
42
TXBC+
Positive LVDS clock for B channel
43
TXBC-
Negative LVDS clock for B channel
44
GND
Ground
45
TXB2+
Positive differential LVDS data bit B2
46
TXB2-
Negative differential LVDS data bit B2
