29 September 1997 – Subject To Change
Internal Architecture
2–11
21164PC Microarchitecture
The DTB also supports the optional superpage extensions that are enabled using
ICSR<SPE>. The DTB superpage maps provide virtual-to-physical address transla-
tion for two regions of the virtual address space, as described in Section 2.1.1.4.
PALcode fills and maintains the DTB. The operating system, using PALcode, must
ensure that virtual addresses be mapped either through a single DTB entry or through
superpage mapping. Multiple simultaneous mapping can cause UNDEFINED
results. The only exception to this rule is that any given virtual page may be mapped
twice with identical data in two different DTB entries. This occurs in operating sys-
tems, such as OpenVMS, which utilize virtually accessible page tables. If the level 1
page table is accessed virtually, PALcode loads the translation information twice;
once in the double-miss handler, and once in the primary handler. The PTE mapping
the level 1 page table must remain constant during accesses to this page to meet this
requirement.
2.1.4.2 Load Instruction and the Miss Address File
The MTU begins the execution of each load instruction by translating the virtual
address and by accessing the data cache (Dcache). Translation and Dcache tag read
operations occur in parallel. If the addressed location is found in the Dcache (a hit),
then the data from the Dcache is formatted and written to either the integer register
file (IRF) or floating-point register file (FRF). The formatting required depends on
the particular load instruction executed. If the data is not found in the Dcache (a
miss), then the address, target register number, and formatting information are
entered in the miss address file (MAF).
The MAF performs a load-merging function. When a load miss occurs, each MAF
entry is checked to see if it contains a load miss that addresses the same Dcache (32-
byte) block. If it does, and certain merging rules are satisfied, then the new load miss
is merged with an existing MAF entry. This allows the MTU to service two or more
load misses with one data fill from the CBU.
There are six MAF entries for load misses and four more for IDU instruction fetches
and prefetches. Load misses are usually the highest MTU priority.
Refer to Section 2.5 for information on load-merging rules.
2.1.4.3 Dcache Control and Store Instructions
The Dcache follows a write-through protocol. During the execution of a store
instruction, the MTU probes the Dcache to determine whether the location to be
overwritten is currently cached. If so (a Dcache hit), the Dcache is updated. Regard-
less of the Dcache state, the MTU forwards the data to the CBU.