29 September 1997 – Subject To Change
Initialization and Configuration
7–7
Serial Read-Only Memory Interface Port
If srom_present_l is asserted during setup, then the system performs an SROM load
as follows:
1.
The srom_oe_l signal supplies the output enable to the SROM.
2.
The srom_clk_h signal supplies the clock to the ROM that causes it to advance
to the next bit. The cycle time of this clock is 126± times the CPU clock period.
3.
The srom_data_h signal inputs the SROM data.
7.4.1 Serial Instruction Cache Load Operation
All Icache bits, including each block’s tag, address space number (ASN), address
space match (ASM), valid, and branch history bits, can be loaded serially from off-
chip serial ROMs. Once the serial load has been invoked by the chip reset sequence,
the first 8KB of the Icache is loaded automatically from the lowest to the highest
addresses. The second 8KB of the Icache cannot be loaded serially. The tag valid bits
for this bank should reflect this.
The automatic serial Icache fill invoked by the chip reset sequence operates inter-
nally at a frequency of 126 × CPU clock period. However, due to the synchroniza-
tion with the system clocks, consecutive access cycles to SROM may shrink or
stretch by a system cycle. For example, for a system with a system clock ratio of 15,
the time between the two consecutive SROM accesses may be anywhere in the range
111 to 141 CPU cycles. The SROM used in the system must be able to support
access times in this range. Refer to Section 9.4.4 for additional SROM timing infor-
mation.
The serial bits are received in a 256-bit-long fill scan path, from which they are writ-
ten in parallel into the Icache address. The fill scan path is organized as shown in the
text following this paragraph. The farthest bit is shifted in first and the nearest bit is
shifted in last. The data and predecode bits in the data array are interleaved. The
placeholders are merely for padding the record to a power of 2 and are “don’t cares.”
