Digital Equipment 93959-1 Technical Manual Download Page 204

Page: 204 / 318

Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

Summary of Contents for 93959-1

Page 1: ...nderutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In...

Page 2: ...EK VT240 TM 001 VT240 Series Technical Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 3: ...VT240 TM 001 VT240 Series Technical Manual Prepared by Educational Services of Digital Equipment Corporation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg co...

Page 4: ...ference will not occur in a particular installation If this equipment does cause interference to radio or television reception which can be determined by turning the equipment off and on the user is e...

Page 5: ...ates Operating Modes VT100 Mode VT200 Mode Seven Bit VT200 Mode Eight Bit VTS2 Mode ReGIS Mode 4010 4014 Mode Controls Controls CONTROLS INDICATORS AND CONNECTORS General System Box VS240 Monochrome M...

Page 6: ...ntrol Gates Address Latch Decode Memory Map Memory Access Read Only Memory ROM RAM Ra ndom Access Memory I O Buffer I O Decode Keyboard Interface I F 8251A USART Internal Circuits 8251A USART Addresse...

Page 7: ...8085A 2 Microprocessor Device Transactions Character Processor CP Memory Video Access Graphics Processor PD7220 Graphics Display Controller GDC Internal Circuits PD7220 Graphics Display Controller GDC...

Page 8: ...Mode Keyboard Receive Mode Reset Signal for 81351 Microprocessor Hardware Keyboard Identification ID Voltage Supplies Keyboard Programming Keyboard Layout and Key Identification Modes Special Consider...

Page 9: ...and Fan Components Power Supply 1 PSI DC Power Input Connector Jl 5 V Input Circuit 12 V Input Circuit 12 V Input Circuit DC Power Okay Circuit INTEGRAL MODEM OPTION General Compatibility and Feature...

Page 10: ...e Data Loopback Test RDL 10 16 Test Mode Indicate Test IND 10 16 APPENDIX A SPECIFICATIONS APPENDIX B VT240 VT102 DIFFERENCES APPENDIX C VT240 VT125 DIFFERENCES APPENDIX D REGISTER BIT VALUES APPENDIX...

Page 11: ...erminal System Block Diagram CPU Logic Block Diagram CPU Block Diagram TIl Internal Block Diagram Power Up Sequence TIl Timing Diagram TIl 16 Bit Dynamic Read Transaction Diagram TIl 16 Bit Dynamic Wr...

Page 12: ...Read Write Transactions Character Processor CP Memory Block Diagram Video Access Block Diagram Graphics Processor Block Diagram PD7220 GDC Block Diagram PD7220 GDC Timing Diagram CPU CP Write 6 7 6 8...

Page 13: ...Example VT240 Series Terminal System Block Diagram Monochrome Monitor Exterior View Monochrome Monitor Block Diagram Monochrome Monitor System Communications Diagram Composite Video Signal Representa...

Page 14: ...Upper CTUR and Lower CTLR Registers 2681 DUART Auxiliary Control Register ACR 2681 DUART Interrupt Status Register ISR 2681 DUART Interrupt Mask Register IMR 2681 DUART Output Port Configuration Regi...

Page 15: ...Circuit I O Addresses PD7220 GDC Commands Summary Video Output Map VOM Addressing Intensity Definition for Output Map Outputs Video Logic Signal Description Video Logic Schematic References Keyboard M...

Page 16: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 17: ...ction introduces the VT240 Series terminal Chapter 2 all VT240 connectors Controls Indicators and Connectors describes Series terminal controls indicators and Chapter 3 System Overview provides an ove...

Page 18: ...ipment Corporation publications refer to Related Documentation The final part of this provide specifications programming reference data manual is made up of Appendices which differences between termin...

Page 19: ...VR241 A Series Documentation VT241 A Series Installation Owner s Guide VT241 A Series Installation Guide VT241 A Series Mini Maintenance Manual VT241 A Series Pocket Service Guide Maintenance Print S...

Page 20: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 21: ...ng In addition the terminal also has a 4010 4014 mode to support industry standard Tektronix software packages 1 2 PHYSICAL DESCRIPTION The terminal Figure 1 1 consists of three units a monitor a keyb...

Page 22: ...inals SYSTEM BOX L KNTEGRAl MaDEJ OPTiON POWER J SUPPLY PS LOGIC BOARD ASSEMBLY MA 1442 83 Figure 1 2 VT240 Series Terminal Block Diagram 1 2 Artisan Technology Group Quality Instrumentation Guarantee...

Page 23: ...e VR201 a 12 inch monochrome monitor The VT241 uses the VR241 a 13 inch color monitor 1 3 DISPLAY CAPABILITIES Text and graphic image display is done by raster scan of an 800 X 240 picture element pix...

Page 24: ...and one mode executes Digital private functions VT52 mode The following major text capabilities are available within these various modes 24 rows of text with either 80 or 132 characters per row charac...

Page 25: ...a pixel to pixel basis at a given time VT241 Four monochrome shades displayable on a pixel to pixel basis at a given time VT240 COMMUNICATION ENVIRONMENT The terminal s major communications features i...

Page 26: ...keys that have a direct functional counterpart on the VT102 keyboard All data is restricted to seven bit format and only ASCII U K or special graphics characters are generated 1 6 2 VT200 Mode Seven B...

Page 27: ...or special graphics characters are generated 1 6 5 ReGIS Mode ReGIS mode is a graphics instruction set available when the terminal is in VT100 mode or either VT200 mode ReGIS provides a full range of...

Page 28: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 29: ...he system box on or off EIA Host Port Connector connects the system box to a host computer either directly or via an external modem rz s INTEG RAL MODEM OPTION PANEL AC T CONNECTOR 0 I i FUSE 0 o IQ l...

Page 30: ...240 or to the connector at the VR24l color monitor end of the system box connection cable for the VT24l AC Input Connector system box connects the power cord to the Fuse protects the system box from e...

Page 31: ...rols Indicators and Connectors Keyboard monitor box Connector The keyboard connects the keyboard to the can also connect to the system Pushbutton releases a post that drops to provide a 30 degree tilt...

Page 32: ...lowing Power Switch turns the monitor on or off Video Cable Connectors connect the system box to the monitor POWER OK INDICATOR MA_0039_84 Figure 2 3 VR241 Monitor Controls Indicators and Connectors F...

Page 33: ...zation source to the monitor Impedence Switch selects 75 ohm or high impedence Voltage Select Switch matches the input voltage selected for the monitor to the voltage supplied at by the wall outlet CA...

Page 34: ...I _ Screen Screen Set Up Talk Break F6 F7 F8 F9 FlO ESC BS IF F14 _ _ _ _ F17 F18 F19 F20 ooooonooooonOOoonBI Do Inoooo DD u uuuu D D DDD D D DLJ D DDDD D IShih 1 EJDD ISh h 1 Dnte 1 I 1 10 Figure 2...

Page 35: ...h another key generates either the key s shifted value for alphanumeric and two symbol keys or as with some function keys generates a predefined control function such as SHIFT and x which generates a...

Page 36: ...lication program in effect 2 5 3 Auxiliary Keypad The auxiliary keypad Figure 2 7 is used primarily to enter numeric data However some keys on this keypad PFl PF2 PF3 and PF4 can have different functi...

Page 37: ...if BREAK generation is enabled in set up SHIFT and BREAK initiates a disconnect while CTRL and BREAK sends the answerback message to the host F11 ESC generates an ESC character in either VT100 or VT5...

Page 38: ...alk F6 F7 FS F9 FlO ESCI F12 SS F13 IF F14 Hold Screen lock Compose Walt F17 F18 F19 F20 I DDDDDnDDDDDnDDDDnBI Do InDDDD Figure 2 8 Top Row Function Keys and LEDs Artisan Technology Group Quality Inst...

Page 39: ...the SHIFT or CTRL keys are depressed because these keys do not generate characters only modify characters generated by other keys When the WAIT indicator is on characters from the keyboard will be lo...

Page 40: ...or for the BCC01 cable 12V IN PIN 3 SERIAL OUT PIN 4 SERIAL IN Pli 1 CABLE CONNECTOR WIRING KEYBOARD END SIGNAL SERIAL IN GROUND 12 V IN SERIAL OUT PIN NO 1 2 3 4 PIN NUMBERS 4 3 2 1 MONITOR END SIGNA...

Page 41: ...ressing the SET UP key to Examine or change terminal operating characteristics such as transmit and receive speeds Transfer from on line mode to local mode or from local mode to on line mode While in...

Page 42: ...dem Communication is through a direct line link with the host either through the EIA host port or the 20 rnA port External Modem Communication is with a remote host using the external modem linked to...

Page 43: ...l block diagram of the terminal This diagram shows the following major components and or logics CPU logic Video logic System communication logic Integral modem option Power supply Keyboard Monitor SYS...

Page 44: ...mode VT52 mode and serial I O handling Video Logic The video logic develops the video output signals necessary to drive the terminal monitor The video logic consists of the following major circuits c...

Page 45: ...l modem consists of the following major circuits components Two four pin telephone jack connectors for interfacing with the telephone line 3 3 5 Handshake circuits to control communication between the...

Page 46: ...ightness and contrast controls The VR241 also contains its own power to the operating voltages required develops its operating voltages from power supply in the system box 3 4 SYSTEM INTERACTION suppl...

Page 47: ...D FROM THE KEYBOARD TO THE CPU LOGIC 2 IF SCREEN DISPLAY IS TO BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY 3 IF DATA IS TO BE OUTPUT TO AN AUXILIARY DEVICE CPU LOGIC DIRECTS TRANSFER OF...

Page 48: ...TO ALTER DISPLAY MA 144 83 System Interaction in Local Printer Port as Input Port 1 DATA IS TRANSFERRED FROM THE KEYBOARD TO THE CPU LOGIC 2 DATA IS TRANSFERRED FROM THE CPU LOGIC TO THE HOST VIA EITH...

Page 49: ...OR THE AUXILIARY DEVICE VIA PRINTER PORT PORTION OF THE SYSTEM COMMUNICATION LOGIC IF DATA IS PRESENT FROM BOTH SOURCES AND BOTH ARE ENABLED CPU LOGIC WILL DETERMINE WHICH DATA TO PROCESS FIRST 2 DATA...

Page 50: ...CE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION LOGIC System Interaction in On Line Printer Port as Output Port MA 1450 83 1 DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE HOST VIA EITHER EIA H...

Page 51: ...O LOGIC TO ALTER DISPLAY MA 1452 83 System Interaction in On Line Printer Port as Inactive or Output Port Q V 1 DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST VIA EITHER INTEGRAL MODEM OR EIA HOST...

Page 52: ...BE AFFECTED CPU LOGIC DIRECTS VIDEO LOGIC TO ALTER DISPLAY MA 1454 83 System Interaction in On Line Printer Port as Input Port Q V 1 DATA IS TRANSFERRED TO THE CPU LOGIC FROM THE HOST VIA EITHER INTEG...

Page 53: ...F THE SYSTEM COMMUNICATION LOGIC 2 DATA IS TRANSFERRED BETWEEN THE CPU LOGIC AND THE AUXILIARY I O DEVICE VIA PRINTER PORT PORTION OF SYSTEM COMMUNICATION LOGIC MA 1456 83 System Interaction in On Lin...

Page 54: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 55: ...omponents Directs system communication logic keyboard module operation video logic and Initializes system at power up and executes self test programs SYSTEM BOX Figure 4 1 I I VIDEO LOGIC LOGIC __ L _...

Page 56: ...ory ROM Nonvolatile random access memory NVR Volatile random access memory RAM Memory map Interrupt control Command register Clock generator I O buffer I O decode Keyboard interface I F 1 CPU 1 CPU I...

Page 57: ...ons desired Initializes the system programming stored in terminal s readiness on ROM power up and executes test memory to determine the FROM CLOCK GENERATOR XTAL 1 Figure 4 3 Tll BCLR All H AI7 H DALO...

Page 58: ...description of the values defined by the external mode register Address Register contains the RAM address to be accessed by the next read or write operation Clock Buffers buffers timing input from cl...

Page 59: ...RESS INTE RRUPT BUFFERS n AIO H AI7 H 16 BIT INTERNAL BUS IINSTRUCTION REGISTER I I STATUS REGISTERl 1 INTERNAL CONTROL MODE REGISTER I CONTROL IDATA ADDRESS I BUFFERS DCAS L R WLB H DRAS L SELO 1 R...

Page 60: ...to execute one micro instruction The microcycle performs all the functions necessary for transferring data internally and externally and for calculating values Each read write refresh and NOP microcyc...

Page 61: ...T FETCH 89 ts AFTER PUP H AT ADDRESS 000000 4 INIT L 30 ns AFTER BCLR L A MAPPER OFF B 8085 RESETS C KYBD UART RESET LPBK OFF D COMM SEL EIA CONN E HOST PRTR UART RESET DISABLES Tx Rx STOPS CTR TIMER...

Page 62: ...ns 501 PI H 1 107 6 nS 234 ns l R WLB X MEM MAP x 68 nsF DRAS L __ 94 9 ns 584 ns DCAS L 1 146 ns 324 5 ns PI L 1 123 ns l 249 ns NOTES 1 RAS PRECHARGE 151 ns 2 MAX RD DATA AVAIL 493 ns 3 CAS H TO DA...

Page 63: ...AS L CAS L RAS L PI R WHB H R WLB H y ADDRESS STROBES MA 4849 MA 0134 84 Figure 4 7 Tll 16 Bit Dynamic Read Transaction Diagram 4 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S...

Page 64: ...WHB R WLB RIWHB H RIWLB H Figure 4 8 y J ADDRESS STROBES DATA OUT v DATA STROBES MA 0137 84 TIl 16 Bit Dynamic Write Transaction Diagram 4 10 Artisan Technology Group Quality Instrumentation Guarantee...

Page 65: ...4 9 AI 1 4 RAS L CAS L PI Figure 4 10 REFRESH ADDRESS MA 4865 MA 0136 84 TIl Refresh Transaction Diagram INT REQUEST MA 4863 MA 0138 84 TIl ASPI Transaction Diagram 4 11 Artisan Technology Group Quali...

Page 66: ...s in response to CPU control and flag signal signals The control gates Figure 4 12 consist of the following two decoding circuits Output Flag Decode Gates decode SEL0 SELl inputs to enable either refr...

Page 67: ...L9 H 0 Dynamic memory DAL10 H 1 4K 16K memory DAL11 H 0 16 bit bus DAL12 H 1 User DAL13 H DAL15 H Octal 5 Start address of 000000 restart 000004 Table 4 2 Output Flag Decode Gates Truth Table Input Va...

Page 68: ...O h_ _ _ _ _ L y TO RAM DRAS L 1Fc FROM CPU IBUSOP L L f _________ r TO I O DECODE L_______ R WHB H R WLB H PI H PI L TO I O BUFFER TO RAM TO NVR TO I O DECODE TO CMD REG TO MEM MAP I TO SYSTEM COMM...

Page 69: ...address from address latch and data from I O buffer inputs to develop values for the most significant 8 bits of the mapped 20 bit address The memory map Figure circuits conponents 4 14 consists of th...

Page 70: ...from the map adders gate for write operation One adds map input mux inputs to RDA0 H RDA3 H inputs from the I O buffer and the other adds map input mux signals against RDA4 H RDA7 H inputs from the I...

Page 71: ...w inputs both true with the MAP ON H output acting as an input select signal for the map output mux Map Output Mux consist of two mux devices each enabled by MAP ON H high true to pass map adders inpu...

Page 72: ...OM can consist of up to six separate ROM devices with a total ROM space of 96K bytes Figure 4 17 ROM 1 CS L MEMORY ROM 2 CS L TO ROM ACCESS ROM 3 CS L DECODER RAM CSL TO RAM MDA15 H MDA19 H MDA18H IS...

Page 73: ...e 4 6 the TIl timing diagram and Figure 4 7 and Figure 4 8 the TIl read write transaction diagrams During refresh transactions only row addressing is required RAM is refreshed after 128 refresh cycles...

Page 74: ...high developed from MUX H input to the input mux during refresh transactions The output mux selects A inputs MDA16 H MDA14 H and MDA12 H when RAM MUX H is false low developed from RRAS L input to the...

Page 75: ...AL 0 DAL 1 DAL 2 DAL 3 DAL 4 DAL 5 DAL 6 DAL 7 GATES RAM H I C A S L lr r r r r FROM Tll R WHB H Figure 4 20 D15 D14 D13 D12 Dll Dl0 D9 NOTE ADDRESS AND RRAS L INPUTS ARE NOT SHOWN RAM Devices Array 4...

Page 76: ...by the I O buffer Data is transferred from the RDA lines to the DAL lines only when both IO EN Hand RD H are true both high Data is transferred from the DAL lines to the RDA lines for all other condit...

Page 77: ...MAP CS L MEM MAP SEL L CMD REG RD L TO tMEM JMAP TO CMD REG _ TONVR RD BUF L WR BUF L 8085 RESET L VIDEO MEM MAP L FROM WLB L CONTROL jTO LOGIC WR 8UF L KYBO L GATES TO H O S T P RT R L t c c _ KYBD...

Page 78: ...signal to WLB L Graphics R W Gates consists of the AND gate and two OR gates The AND gate generates a VID ACCESS L low output true whenever either GRD L or GWLB L is low true The OR gates tie GRD L to...

Page 79: ...174131313 Video logic VID ACCESS L 173131313 174131313 Video logic G8e85 L 175eex Video logic RD BUF L 175131313 Video logic WR BUF L 17513132 Video logic 81385 RESET L 17513134 Video logic NVR L 176X...

Page 80: ...sed for testing The loopback gates are enabled by 825lA output LPBK EN L developed from the DTR output of the 8251A to route transmit tx data back to the 8251A as receive rx data Keyboard Transmit Dat...

Page 81: ...251A internal circuits Data Bus Buffer buffers data transfer between the TIl as RDA0 H RDA7 H and registers within the 8251A command status transmit data and receive data register devices Modem Contro...

Page 82: ...operating parameters as well as a status register to report operating conditions to the TIl and circuits required to determine what type of access is being attempted by the TIl The TIl can attempt th...

Page 83: ...te bytes of programming The first byte written defines the mode instruction format the second byte written defines the command data for that mode format Both bytes are written to the 825lA command reg...

Page 84: ...1A USART Transmit Data TxD Timing Diagram OVERRUN ERROR STATUS BIT KYBD INTR2 L LDA2 H COMM WR L COMM RD L RxD L NOTES KYBD INTR2 L IS SHOWN ENABLED FOR RX READY CONDITION 2 TRxR IS A MAXIMUM OF 8 CLO...

Page 85: ...e EPROM effectively reprogramming the EPROM At the next power up sequence the new EPROM values are transferred back into the NVR RAM and these values now determine the terminal s starting parameters T...

Page 86: ...functionality Read Terminal Operating Parameters RD H is true high DCAS Land NVR L are both low both true and LDAl H LDA8 H define the portion of the NVR device s RAM memory to be affected write Term...

Page 87: ...y PI L low true to output as All H AI4 H the four bit code at the memory location defined by inputs from the interrupt buffer PROD TEST2 L input is always high or false as it is tied to 5 V with this...

Page 88: ...S L low true condition and those values read out of the register as RDA0 H RDA7 H whenever a low is input from the command register gate Later in this chapter Table 4 6 describes the signals shown in...

Page 89: ...HZI TOCPU C L K2 H 3 68 64 _ _ TO KYBD IIF TO SYSTEM COMMUNICATION LOGIC MA 016 84 Figure 4 30 Clock Generator Block Diagram 4 3 SIGNAL DESCRIPTIONS Table 4 6 gives descriptions of all the signals ide...

Page 90: ...input interrupt data from the interrupt control Control output from control gates disabling I O decode when TIl is in ASPI cycle 3 6864 MHz output from clock generator which provides general timing f...

Page 91: ...ious circuits and components for operation Control signal output from TIl used to enable various circuits and components for operation Control signal output from the control gates whenever a read acti...

Page 92: ...munication logic and indicating DUART is ready to process data for a host device Select signal output from I O decode enabling TIl access of DUART in system communication logic for read write transact...

Page 93: ...RxD L Also used as status input to command register to report loopback condition Enables memory map to select mapped address values for output when true high and regular address values when false low...

Page 94: ...nd status registers within the system communication logic True low status input to command register from video logic whenever a monitor is hooked up to the system Selects signal output from I O decode...

Page 95: ...te control outputs from TIl defining type of read write transaction to occur Outputs from RAM address buffer which provide least significant four bits of column and row addresses to RAM for read write...

Page 96: ...efresh activity and false low output when address value is to be selected for RAM read write transaction Control signal output from control gates true high for read transactions Select signal output f...

Page 97: ...riginating at the keyboard module Til output providing two bit code to control gates with code value defining the type of transaction to occur Status signal input to command register low when Til has...

Page 98: ...is to occur Select signal output from I O decode enabling Tll access of data buffer in video logic for write transaction Clock input to Tll from clock generator 7 3728 MHz Operating output to keyboard...

Page 99: ...RAM OAS ga tes RAM devices ROM devices TIl WR BUF GATE 8251A UART Logic Board Reference Numbers E41 E43 E45 Y2 E90 E48 E62 E91 E69 E47 E72 E90 E75 E74 E55 E68 E47 E54 J6 E27 E45 E62 E66 E67 E31 E69 E...

Page 100: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 101: ...on or the host via the EIA host port or 20 mA port SYSTEM BOX Figure 5 1 VIDEO LOGIC LOGIC __ L _ _ __ _ SYSTEM COMMUNICATION LOGIC EIA PRINTER 20 rnA HOST PORT PORT PORT OPTIONAL HOST COMMUNICATIONS...

Page 102: ...d from the system communication logic 5 2 MAJOR CIRCUITS COMPONENTS Figure 5 2 is a block diagram that identifies the following major circuits components that make up the system communication logic 5...

Page 103: ...f o l J S J U CONTROLS MUX EIA HOST IIF L _ J L ___ J MA 0155 84 Figure 5 2 System Communications Logic Block Diagram 5 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www...

Page 104: ...2681 DUART s internal circuits and the CPU logic data lines TO FROM CPU LOGIC DATA LINES TO FROM CPU LOGIC DAO H RDA7 COMM RD L COMM WR L LDA2 H LDA5 HOST PRTR L HOST INTR1 L 2681 HOST INTR2 L DUART T...

Page 105: ...a Channel B Printer data to serial data port receive data RxD DATA BUS BUFFE RS DRD L W L B L_ OPERATION HOST PTR L CONTROL LDA2 H LDA5 H INIT H CLK 2 H TIMER INTR L HOST INTR2 L PRTR INTR 1 L PRTR IN...

Page 106: ...to program control read status and data transfer to and from the DUART CPU logic does this by addressing specific devices LDA2 H LDA5 H for read COMM RD L or write COMM WR L operations while the DUART...

Page 107: ...hannel Printer channel Printer channel Printer channel Printer channel Input port Output port Timing Output port Timing Output port 5 7 Register Mode register 1 and 2 Mode register 1 and 2 Status Data...

Page 108: ...OR INTEGRAL MODEM COMMUNICI TION 5 HOST DTR L IS NOT USED BY THE 20mA I F 6 PRTR DSR L WILL BE SAMPLED BEFORE TxD B OUTPUT IF PRTR DSR L WAS NOT TRUE AT 2681 DUART POWER UP MA 0145 84 2681 DUART Trans...

Page 109: ...Modem Control Circuits following breakdown of comm modem control Figure 5 7 shows the Communication Control Register COMM CTRL REG contains a write register for storing control data written by the CPU...

Page 110: ...OT 0 MOD SW HK H l CTRL TEST IND H u RD CCT H I I REG MOD A B L I I MODE SEL H DIAL TONE DET H I I I I MOD CTKL ROAD RDA5 RDA6 WR REG TI I WR MOD CTR L L I _ _ L IJI _ _ RD COM M CTRL LDAl LDA2 I I CO...

Page 111: ...CPU logic accesses various status LDAI while comm modem control registers to program control or read The CPU logic does this by addressing a specific register H LDA2 H for read ORO L or write WLB L o...

Page 112: ...kdown of the comm mux Comm Output Mux converts DUART data and ready signals to data and ready signals to the selected interface only the data signal is passed on to the 20 rnA interface Comm Input Mux...

Page 113: ...gram TO FROM DUART PRTR DTR L TxD B RxD B PRTR DSR L Figure 5 9 5 I LINE 2 BUFFERS r 3 r r NOTE J2 PIN 1 IS NOT CONNECTED ON LOGIC BOARD J2 PINS 4 7 AND 9 ARE NOT USED J2 CD 108 2 S1 2 BA 103 D1 BB 10...

Page 114: ...connected to the 20 rnA port Figure 5 11 shows the following breakdown of the 20 rnA interface Transmit Optoisolator provides isolation between the TTL level transmit data signal 20 rnA TxD L at the...

Page 115: ...4 CB 106 M2 CA 105 SE CH 111 S4 AB 102 E2 MA 01S2 84 Figure 5 10 EIA Host Interface IfF Block Diagram TO FROM COMM MUX 20mA TxD L 20mA RxD L NOTE TRANSMIT OPTOISOLATOR 12A RECEIVE OPTOISOLATOR J4 PINS...

Page 116: ...D2 DSR L 3 28 MOD2 CTS L MOD2 RxD L 4 27 MOD2 DTR L MOD2 SI L 5 26 TEST IND H MOD2 TxD L 6 25 RDL TEST H MOD2 SPD SEL H 7 24 ANL TEST H GND 8 23 NOT USED DATA AVAIL L 9 22 OH M H OH D L 10 21 SW HK H...

Page 117: ...nic AA 191 El AB 192 E2 ANL TEST H BA 103 Dl BB 104 02 CA 105 SE NOTE The reference listing is based on Rev C of the schematics CS54l5495 9 l System Communication Logic Signal Descriptions Signal Name...

Page 118: ...ready for communication activity Indicates integral modem senses audio path to telephone line is ready Indicates terminal is ready for communication activity Indicates external modem senses good comm...

Page 119: ...host CSL0 H C SLl H both low or 20 rnA CLS0 H LOW CSLI H high Requests data path through integral modem Indicates integral modem senses telephone line ready for dialing Not currently used Enables rea...

Page 120: ...or external modem is ready to receive transmit data buffered CB 106 M2 Indicates host or modem is ready for communication activity Indicates terminal is is ready to transmit or receive Indicates host...

Page 121: ...TR L both low Defines integral modem to use 9 bi t high or l bit characters low Defines integral modem emulation of BELL 212A high or BELL l 3 V 21 low Indicates good comm line has been detected by ei...

Page 122: ...m serial receive data Selects mode for integral modem operation as either originate low or answer high Low whenever integral modem is installed External modem signal defining receive transmit speeds o...

Page 123: ...ng each character buffered CC 107 Ml Active ready output to printer port device from power on buffered CD 108 2 S1 2 Indicates printer receive data is present Indicates DUART is ready for printer tran...

Page 124: ...rial transmit data Indicates integral modem is in test mode Programmable interrupt Printer serial data buffered BA 103 Dl 5 V operating voltage Enables write outputs WR COMM CTRL L or WR MOD CTRL L wh...

Page 125: ...lk inverter MOD DOM EUR inverter Printer I P buffers Receive optoisolator Transmit optoisolator Logic Board Reference Numbers Schematic Page Coordi na te E60 7 E59 7 E33 7 E34 7 e57 5 E54 17 E24 8 E29...

Page 126: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 127: ...e CPU logic The CPU logic communicates with the video logic to initialize operation define patterns define modes define output color values and identify new display data SYSTEM BOX Figure 6 1 VIDEO LO...

Page 128: ...s processor and related circuits to read status program operating parameters or provide graphics image data for display The CP processes text characters for display after the CPU defines which charact...

Page 129: ...J I TIMING AND CONTROLS CLOCKS AND CONTROLS G 70 J f o I I I I I I I I IVIDEO IOUTPUTS I I I ENABLES o w o L_______________ _____________ _____ J MA 0362 B4 Figure 6 2 Video Logic Block Diagram Artisa...

Page 130: ...cked into the buffer by the transition of the 85WR BUF L trail edge and read out by RD BUF L going low true Address Latch Generates the address used by 8085A 2 85LA0 H through 85LA7 H to access either...

Page 131: ...85A 2 internal circuits Serial I O Control is used for handshaking between the 8085A 2 and the TIl Interrupt Control RST 5 5 RST 6 5 interrupt condition access the relevant in CP memory monitors inter...

Page 132: ...logic Read write of CP memory Read write of graphics processor I O device circuits The CPU reads data from the 8085A 2 to determine operating conditions The CPU writes data to the 8085A 2 to define t...

Page 133: ...ocessor I O circuits Note that although memory access can occur at any time the 8085A 2 is limited to I O access only during vertical sync time defined by GVS Hand GBLK H interrupt inputs Later in thi...

Page 134: ...that contains firmware that directs 8085A 2 operations as well as character pattern data NOTE CP ROM can consist of a single 32K device or two ROM devices with up to 32K storage If a 32K ROM is used i...

Page 135: ...UF L Only one processor can use the video access circuit at given time Control over enabling access is the VID ACCESS L signal from the CPU logic When VID ACCESS L is low true the CPU has access when...

Page 136: ...UF L 85WRBUF L VIO ri V RD GDC L tt RD VDM L VIO RD INIT CBADDR L iWRGDCL I WR VOM L IWR CHAR BUFF L WR RATWWLT L IWR MASK L I V WR VPAT L IWR LU L I WR REGO L WR REG1 L I WR HB SCROLL D A L I WR LB S...

Page 137: ...es the signals shown in Figure 6 7 Table 6 2 Video Access Circuit I O Addresses CPU Address CP Address Signal Octal Hex Destination Device RD GDC L 173000 173002 00 01 GDC WR GDC L 174000 174002 00 01...

Page 138: ...croprocessor device FIFO Buffer is a 16 byte device that stores command information communication between the system IIF and FIFO is on a separate bus from the PD7220 internal bus Command Processor ac...

Page 139: ...MUX DEVICES MA 0368 84 Figure 6 8 Graphics Processor Block Diagram RDGDC L WRGDC L VAO H CK 2MZ L GND 5V SYSTEM I F FIFO BUFFER COMMAND PROCESSOR PARAMETER RAM Figure 6 9 GBLK H VIDEO GHS H SYNC GENE...

Page 140: ...73002 for a write of parameter data to GDC FIFO WR GDC L low and VA0 H high or a read of status data from GDC status register RD GDC L low and VA0 H high All write operations are to the GDC FIFO with...

Page 141: ...nes per video field Generate and output vertical sync Cursor and character characteristics command followed by three parameter bytes parameter bytes define cursor on or off lines per character row cur...

Page 142: ...direction write data into display memory with data transfer defined as a word and RMW cycle logical operation defined as reset to zero Mask register load command followed by two parameter bytes defini...

Page 143: ...address values CPU CP read of data from display memory command defining data read cycle to be a word with first low then high bytes read CPU CP read of cursor position with position of word and dot a...

Page 144: ...nchronization Figures 6 l through 6 15 are timing diagrams for various GDC operations Later in this chapter Table 6 6 describes the signals shown in these diagrams VAOH WRGDCL VDBOH VDB7H t j I TWCY S...

Page 145: ...DC Timing Diagram CPU CP Read Transaction 2 X CK 2MZ L GADO H GAD 14 H GAD15 H A16 GRAS L TDD GHSH GBLK H _______J_ ________A GVS H SYMBOL PARAMETER MIN MAX UNITS TAD ADORESS DATA DELAY FROM 2 X CCLK...

Page 146: ...AI HORIZONTAL r 1 H ______ v v v v ___ GAO GAO _ _ __ _ _ _ _ _ _ _ _ _ __ x I J V __ J __ _ x __________ _ x I xl __ l x X x x X __ _ LCOA ROWI ROWI I G BLK L I L GVS L lV l BI VERTICAL MA 0373 84 Fi...

Page 147: ...ESS OUT D GDBENL _ _ _ _ _ RMWH ENDH l ___________________________________ RASL r l RAHH LAS L A15 EPSH A14 EBSH DAD3 DAD3 DATA OUT 0 0 0 0 Figure 6 14 PD7220 GDC Timing Diagram 2 P1ane Write Transact...

Page 148: ...eo DMA write Transaction 6 2 5 Timing and Control Circuits MA 0375 84 The timing and control circuits following circuits Figure 6 16 consist of the Clock generator ROM address counter Timing signal ge...

Page 149: ...r Block Diagram 6 2 5 1 Clock Generator The clock generator provides the basic timing signals used by various video logic components The clock generator Figure 6 17 consists of the following component...

Page 150: ...from STOP gate is true low ROM Address Clock Counter generates address value output A0 H A3 H from CK 16MZ H input Later in this chapter Table 6 6 describes the signals shown in Figure 6 19 6 2 5 4 Ti...

Page 151: ...AND STOP L STOP GATES Figure 6 20 TO BIT MAP MA 0378 84 BEN and STOP Gates Block Diagram ROM TO ADDRESS TIMING SIGNAL CLOCK GEN TO P S CONVERSION MA 0379 84 ROM Address Counter Block Diagram FROM ROM...

Page 152: ...set input from ERASE F F ERASE F F is clocked by the trailing edge of RAS H input with a low output when ERASE L input is true forcing RMW F F to output true RMW control signals Later in this chapter...

Page 153: ...K I L output from BLANK L input and D BLANK buffer which generates D BLANK L output to D A Both are clocked by CK l6MZ H with three clocks needed to reflect any change in BLANK L input at D BLANK L ou...

Page 154: ...ap addressing circuit refer to section 6 2 7 2 Vector pattern register in pattern select circuit refer to section 6 2 10 Depending upon how these various components are programmed the video logic can...

Page 155: ...or the mode select registers Appendix E provides descriptions of the bit values of for the various components used for each of the six write modes 6 2 7 Bit Map Addressing Circuit The bit map addressi...

Page 156: ...DAD3 L low when either ANDed pair are both highs FROM TIMING AND CONTROL FROM TIMING AND CONTROL RMW L FROM MODE SEL GDC H SEL DAD L SELECT DAD LAD eS BL A Nc K eL_ _ _ _ t DECODE R SEL LAD L FROM MO...

Page 157: ...olumn mux Generate LAD1S H LAD16 H output values based on GDC input whenever GDC address values are selected for output to the row column mux LAD1S H LAD16 H values are used at the plane and byte sele...

Page 158: ...mn address values Later in this chapter Table 6 6 describes the signals shown in Figure 6 27 6 2 8 High Low Hi La Byte Select The hi l a byte data GAD0 H GADlS H for circuits GD0 L select circuit sele...

Page 159: ...D7H M _ GAD8H GAD15H AND R M W L ______________ CONTROL FROM EPS L BIT MAP HI LO BYTE MUX I I I MUX TO WRITE DATA SELECT TO BIT MAP WRITE ENABLE SELECT I LB H TO r BITMAP ADDRESSING MA 0388 84 Figure...

Page 160: ...hi lo byte select inputs originating at the GDC GD0 L GD7 L when VEC H is high write Mask Latch generates the write enable outputs during RMW L low with the write enables based on the last enabled mas...

Page 161: ...nsists of the following circuits components Character Pattern Address Counter counts up from a zero starting value loaded by RD INIT CB ADDR L low with incrementing output used as the address value fo...

Page 162: ...PLI ER REGISTER WR PAT MULT L CHARACTER PATTERN BUFFER FROM MODE SELECT SELVPATH PATTERN MULTIPLIER COUNTER IMULTIPLEXER I CLOCK LOAD T _ PATTERN REGISTER IREGISTER I e T Figure 6 30 Pattern Select Bl...

Page 163: ...in Figure 6 30 6 2 11 Logic Unit The logic unit converts data input from the bit map into new write pattern data output to the write data select circuit This conversion is based on the pattern either...

Page 164: ...are opposite values and high to the logic unit when both signals have same value Low to high transition indicates that intensity values for the selected plane are being passed by the intensity select...

Page 165: ...lated internal to the GDC or to the bit map during DMA write mode The write data select circuit following components Figure 6 32 consists of the DMA Buffer generates data output to the bit map when DM...

Page 166: ...Buffer Gates is enabled by VEe L high to pass bit map data outputs to the read back buffer FROM C A S H________ TIMING LLB L AND CONTROL DBEN L FROM MODE VEC L SELECT GADO H GAD15 H TO WRITE DATA SELE...

Page 167: ...4 consists of the following circuits components Bit Select BS Gate gates EBS 1 and DAD3 1 input with Scroll enable inputs to generate a BS H value to the gate decoder BS H low for selecting the low or...

Page 168: ...onsists of four eight bit shift storage registers one high byte and one low byte PIS converter for each plane Each register is clocked by CK 64MZ H gated by gate decoder input and controlled by PIS mo...

Page 169: ...r output map values one RAM device for the upper four bits of map0 through map3 and one for the lower four bits Memory is written to by CPU or CP when WR VOM L is low and VOM output when WR VOM L is h...

Page 170: ...BUFFER VOM VDBOH VDB7H WR VOM L SHARES SAME PHYSICAL COMPONENT 2918 VOM BUFFER WITH DBLANK GENERATOR OF TIMING AND CONTROL VBDOH VDB7H VOM READ BACK REGISTER VBOH VB1H VMOH VM1H Figure 6 35 Output Map...

Page 171: ...AP1 BYTE2 1771354 16H 1 13 13 1 MAP1 BYTE3 1771356 17H 1 13 1 1 MAP2 BYTE13 17713613 18H 13 1 13 13 MAP2 BYTE1 1771362 19H 13 1 1 13 MAP2 BYTE2 1771364 1AH 13 1 13 1 MAP2 BYTE3 1771366 1BH 13 1 1 1 MA...

Page 172: ...or or monochrome monitors NOTE J8 can also be used for output of keyboard data output FROM TxDH 15 KY8D R D H IIF x 14 TO MONITOR PRES L 13 CPU 12VC 8 GVS H FROM GDC GHS H 1 6 11 10 9 12 VRO H VR1 H I...

Page 173: ...ar PNP transistor networks that generate the actual video outputs to the monitor VR output stage shown in Figure 6 36 VB output stage identical to VR VG output stage has the 348 ohm resistor replaced...

Page 174: ...w Enables address latch to input 85AD0 H 85AD15 H signals from CPo Buffered version of GO BEN L from GDC True control signals during screen blank periods developed from G BLK H high as synchronized by...

Page 175: ...DC access to GDC data bus lines gated from BGD BEN L buffered version of GO BEN L from GDC and 0 BIN L are both true Control signal output of timing signal generator coordinating GDC access to GDC dat...

Page 176: ...gh to RMW genera tor Coordinates plane select activity with EPS Hand EPS L signals going true on first CAS H true after RAS H true condition Register 0 output defining erase condition when low Gate in...

Page 177: ...tput defining vertical sync period Low input from GDC to video access circuit to access a video logic component for a write transaction Defines background intensity factor to logic unit for either pla...

Page 178: ...originating at GDC SCROLL EN H low input to latched address mux or scroll address counter SCROLL EN H high Timing signals generator output enabling bit map output data to be loaded into bit map read b...

Page 179: ...le bit of plane 3 low order byte PIS converter devices output for single bit of plane 1 high order byte PIS converter devices output for single bit of plane 1 low order byte Vector pattern based on pa...

Page 180: ...O M low for read Low input from CPU to read data from 81385 RD buffer also resets handshaking F F Low output from video access circuit when CPU CP is to access GDC for read Low output from video acces...

Page 181: ...and developed from G BLK H high inverted input synchronized to RAH H Mode select input to piS converter device used to convert plane zero low order byte to serial data P0 LB H Mode select input to PIS...

Page 182: ...ied data written to bit map when SCROLL EN H is high and SEL SD H is low Low outputs from DAD LAD decoder only when SCROLL EN H is low for GDC access of bit map screen is blanked S BLANK L low with SE...

Page 183: ...low Timing signals generator output to piS converter selecting P0 HB H PI HB H output to output map SEL LB L high or P0 LB H PI LB H SEL LB L low Control output from register one used to enable write...

Page 184: ...the timing signals generator used to synchronize blank signal generation Serial keyboard data output routed through the monitor connector J8 Address bits originating at CPU CP and used to address VOM...

Page 185: ...access I O device for read Low to video I O decode whenever CPU CP is to access I O device for write Output map two bit code to D A for mono Output from register zero defining which output map is to...

Page 186: ...ddress counter Low output from video access for CPU CP write of low byte data to scroll address counter Low output from video access for CPU CP write to logic unit register Low output from video acces...

Page 187: ...memory decode to define enable 0 ROM7 ROM7 OE L low or ROM8 ROM8 OE L low and as most significant bit of ROM address Low input to video access from CP R W control when CP is to access I O device for...

Page 188: ...select gate Pattern multiplier counter Schematic Reference Numbers Page Coordinate El133 E136 E137 E1S9 E141 E1713 E177 E137 E1S7 E1S9 El16 9 CS 18 A4 A6 B3 14 D1 D3 18 A1 A4 18 Al E1413 18 CS E1313...

Page 189: ...l 8085 read buffer 8085 write buffer Schematic Reference Numbers E64 E78 E79 E186 E190 E139 E94 E109 E146 E147 E165 E166 E189 E129 E126 E144 E96 E191 E122 E141 E69 El19 E168 E120 E128 El17 E136 E157 E...

Page 190: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 191: ...e CPU logic is full duplex serial and asynchronous at 4800 bits per second bps The communication lines conform to EIA standard RS 423 which applies to imbalanced voltage interfaces SYSTEM BOX Figure 7...

Page 192: ...anged in the following four groups Figure 7 2 Main keypad 57 keys Numeric keypad 18 keys Special function keypad 20 keys Editing keypad 10 keys Figure 7 2 LK201 Keyboard 7 2 KEYPAD NUMERIC KEYPAD Arti...

Page 193: ...nects the keyboard to the video monitor The keyboard transmits four signals to the monitor which pass unchanged to the system box via the video cable Figure 7 3 The four signals are as follows 12 V po...

Page 194: ...I I P DECODER 8 0 1 1 0 I I R 18 1 I 1 T I 2 CONN I KB DRIVE 1 to detect changes in the keyboard KEYBOARD LEOs f 5V LED 4 CONTROL SUPPLY CIRCUIT BEEPER BEEPER 3 CONTROL 2 MS CIRCUIT rn IL BEEP KEYCLI...

Page 195: ...he 8051 controls each of the four indicators The firmware responding to commands received from the CPU turns the indicators on or off 7 3 2 Keyboard Firmware Functions This section describes the keybo...

Page 196: ...ns from the CPU These commands are categorized as transmission commands and peripheral commands Transmission commands contain a mode set command and an autorepeat rate set command Peripheral commands...

Page 197: ...8051 microprocessor and are called KB DATA 0 7 The 8051 scans the 18 drive lines Key closures are detected by reading the eight data lines The complete matrix is scanned every 8 33 ms When a key clos...

Page 198: ...board matrix on the LK201 AA American keyboard Keycap designations are listed for reference only you can compare them to Figure 7 7 A and B B C 3 DRIVE LINES r 2 DATA LINES 1 CONDITIONS ARE SWITCHES B...

Page 199: ...G16 4 F20 G23 N9 022 N8 021 T C17 PREV SCREEN 017 3 PF4 E23 r B17 N5 C2l N7 020 011 2 1 N N Note 1 023 C23 N6 N3 C22 B22 N2 B1B B2l N4 Nl C20 B20 Reserved Cll 1 Note that N0 N9 N_ N refer to the nume...

Page 200: ...J9 9 Reserved Fll Reserved Reserved I K J 8 I GIl Er J8 Dr J8 Cr J8 Br J8 f 8 Reserved MAIN Reserved EXIT U J M SCREEN 7 Gr J8 Gr J9 Er J7 Dr J7 Cr J7 Br J7 7 Reserved CANCEL Reserved RESUME Y H N 6...

Page 201: ...3 3 E03 w D02 1 E01 2 E D03 S C02 Q C01 1 Note that N0 N9 N_ N refer to the numeric keypad 1 D C03 x B02 A B01 3 C B03 B00 z 2 N0 of the numeric keypad can be divided into two keys Normally only the N...

Page 202: ...5 Interrupt Resume Cancel Screen EXit ESC BS IF Options _ _ _ _ ____ F F18 F19 F20 DDDOOnODODDnODODnBI Do II IULJUU f IDD u D JEJ rJ D J D D tu LJLJEJ D E DDDD IShih 1 D J DD IShih 1 i _ i i i i Figur...

Page 203: ...G I 699 IGGGGGGGGGGGI 611 I GGG GGGn I A99 II A0l1oA09 I I A20 IGl J NOTE THE GRAPHIC CHARACTERS ARE SHOWN FOR ILLUSTRATION PURPOSES ONLY AND ARE NOT MEANT TO ASSIGN KEYCAP USAGE OR LEGENDS Figure 7 7...

Page 204: ...binary combinations on the inverter inputs All highs give the softest sound and all lows give the loudest sound The firmware controls the keyclick independently The bell tone is sounded only system co...

Page 205: ...51 PORT 2 74LS05 INVERTERS 12V L l II 5V HIGH E1 r _ _ ______ 5V Figure 7 9 HIGH SIGNAL FROM 8051 PROVIDES PATH THROUGH LAST STAGE OF OPEN COLLECTOR INVERTER TO TURN ON LED MA 0268 B2 Indicator LED Co...

Page 206: ...ures that can be enabled by commands from the CPU There are two categories of features one sets keyboard transmission characteristics and the other controls keyboard peripherals A peripheral command c...

Page 207: ...ll jumpers are installed so the keyboard hardware ID is zero 7 4 7 Voltage Supplies The only voltage sent to the keyboard is 12 V However 5 Vand 10 V are also required These voltages are derived from...

Page 208: ...C99 Horizontal cursors B16 and B18 vertical cursors B17 and C17 Six keys directly above the cursor keys 016 018 and E16 E18 Function keys G99 G03 Function keys G05 G09 Function keys GIl G14 Function...

Page 209: ...ptions Reserved Reserved Help 00 Reserved F17 F18 F19 F20 Reserved Reserved Find Insert here Remove Select Previous screen Next screen Reserved 7 19 Keycode Decimal 086 087 088 089 090 091 098 099 100...

Page 210: ...0 7 157 9D D21 8 158 9E D22 9 159 9F D23 160 A0 E20 PFI 161 Al E21 PF2 162 A2 E22 PF3 163 A3 E23 PF4 164 A4 Reserved 165 A5 Cursor Keys 7 Reserved 166 A6 B16 Left 167 A7 B18 Right 168 A8 8 B17 Down 16...

Page 211: ...hics Keys and Spacebar 1 E00 E01 D01 C01 B01 E02 D02 C02 B02 B00 E03 D03 C03 B03 E04 Tilde 1 Q A Z Reserved 2 W S X Reserved 3 E D C Reserved 4 7 21 Keycode Decimal 179 180 181 182 183 184 185 186 187...

Page 212: ...H 221 DO B136 N 222 DE 1 Reserved 223 OF E137 7 224 E13 0137 U 225 El C137 J 226 E2 B137 M 227 E3 Reserved 228 E4 C138 8 229 E5 0138 I 2313 E6 C138 K 231 E7 B138 232 E8 Reserved 233 E9 E139 9 234 EA 0...

Page 213: ...when the key is first pressed If the key is held down past the specified timeout period usually 31313 to 51313 ms a fixed metronome code is sent at the specified rate until the key is released Down u...

Page 214: ...enerated for an autorepeating keycode or special code may be transmits this special code instead of and then returns to the autorepeated autorepeated is always the last byte The a key is held down Thi...

Page 215: ...n with one command This and other autorepeat commands are grouped with the peripheral commands refer to 6 5 5 3 7 5 2 2 Special Considerations Regarding Down Up Mode If two DOWN UP keys are released s...

Page 216: ...is sent from the system module to enable the keyclick on the C99 key the keyclick is generated refer to section 7 5 5 3 Figure 7 7 shows the positions of these keys The keyclick or bell or both may b...

Page 217: ...ODE ACK PREFIX TO KEYS DOWN MODE CHANGE ACK RESERVED Keycode 179 decimal B3 hexidecimal Keycode 180 decimal B4 hexidecimal keycode 181 decimal B5 hexidecimal Keycode 182 decimal B6 hexidecimal Keycode...

Page 218: ...cessed a indicates that the keyboard has mode change command refer to section RESERVED keycode 7F is reserved for internal use The following four special codes have values below the 6410 range KEYBOAR...

Page 219: ...he corrected four byte power up sequence when the pressed key is released This avoids a fatal error condition if a key is pressed by mistake while powering up The keyboard LEOs are lit during the powe...

Page 220: ...s Mode set Autorepeat rate set Peripheral Commands Flow control Indicator Audio Keyboard ID Reinitiate keyboard Some autorepeat control Jump to test mode Reinstate defaults The high order bit of every...

Page 221: ...an error code Each keyboard LED can be turned on and off The following eight commands control the keyclick and bell sounds Disable keyclick Enable keyclick and set volume Disable CNTL keyclick Enable...

Page 222: ...eat buffer selections Audio volume Control key keyclick To send a peripheral command set the TYPE flag low order bit Bits six three contain a command representation from the chart below Bits two and o...

Page 223: ...Autorepeat Temporary autorepeat inhibit Enable autorepeat across keyboard Disable autorepeat across keyboard Change all autorepeat to down only Other Request keyboard 10 Jump to power up Jump to test...

Page 224: ...tors LEOs Figure 7 12 shows the LED parameter Figure 7 13 shows the LED layout on the LK201 keyboard Audio Figure 7 14 shows the audio volume parameter MA 0179 82 Figure 7 12 Indicator LED Parameter o...

Page 225: ...own Only changes division settings for all autorepeating divisions to down only Request Keyboard IO causes keyboard to send a two byte keyboard ID Keyboard does not jump to powerup Reinitiate Keyboard...

Page 226: ...are parameters Autorepeat Rate Buffer Association If autorepeat mode is selected the system module can transmit a parameter to change the buffer association of the selected division Refer to section...

Page 227: ...1 I 0 1 I 0 1 0 0 0 0 0 1 1 MA 0181 82 Figure 7 16 Set Main Array to Autorepeat Example RATE CHANGE PARAM COMMAND BUFFER NO TYPE A r ____A _ _ 07 06 05 04 03 02 01 00 0 1 I 1 I 1 I 1 I 1 I 1 I 0 0 PAR...

Page 228: ...e that the high order bit is set because it is the last parameter the highest value which may be sent is 124 11111100 The lowest rate which can be implemented by the keyboard is 12 Hz values as low as...

Page 229: ...is unlocked are processed as new keys An error code upon unlocking the keyboard indicates a possible loss of keystrokes to the system module The keyboard stops scanning its matrix when its buffer is...

Page 230: ...uffers The volume levels for the keyclick eight step range The default volume keyclick and bell are the third loudest and bell have an levels for the For the LK201 keyboard the CNTRL control key defau...

Page 231: ...type modular connectors plugs into display monitor PN BCC01 Sculptured key array 30 mm 1 16 in above desk top 105 matte textured finish keys 57 keys 18 keys 20 keys firmware and software driven 10 ke...

Page 232: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 233: ...documents in the introduction to this manual to identify VR241 documents SYSTEM BOX Figure 8 1 LOGIC VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM INTEGRAL COMMUNICATION EIA PRINTER 20 rnA OPTIONAL HOST POR...

Page 234: ...the cabinet to prevent electromagnetic radiation A folding carrying handle is on the bottom rear of the cabinet The glass front of the monitor the CRT face is specially treated to reduce glare The mo...

Page 235: ...SE Figure 8 2 _ CRT FACE CABINET J3 J 1 CONTRAST BRIGHTNESS FOOT FOLDING HANDLE MA 10 500 Monochrome Monitor Exterior View 8 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE...

Page 236: ...signal consists of two types of information video data refer to section 8 3 1 and sync data refer to section 8 3 2 The monitor module provides the following power to the CRT Anode vol tage Grid 1 vol...

Page 237: ...e yoke controls the sweep of the electron beam horizontally across the faceplate each sweep is called a scan line The vertical signal controls the positioning of the beam to a new scan line for vertic...

Page 238: ...a ta Receive Data Send MA 10 113 Monochrome Monitor System Communications Diagram Description None Video signal ground potential Operational voltage ground potential Operational voltage input None Com...

Page 239: ...levels of illumination within the video signal ranging from totally black to maximum brightness Figure 8 5 represents a typical composite video signal and identifies the major terms associated with i...

Page 240: ...est voltage value amplified linearly at the electronics board High limit of display value It equals 100 percent of peak to peak value 1 0 V nominal and is highest voltage value amplified linearly at t...

Page 241: ...50 Hz INT 24 5 SCANS lrLJin1 VERTICAL INTERVAL TIME_ n I START OF ODD FIELD H BLANK 11 84 s 50 ns F 12 34 s 50ns 80 COLUMN 132 COLUMN V I H PERIOD 63 56 s 01 NOTES IN NON INTERLACED OPERATION THE EVE...

Page 242: ...vertical retrace activity Delay value between start of blanking and start of sync pulse Period of time the actual synchronizing of the vertical deflection circuitry on the electronics board takes plac...

Page 243: ...8 6 YOKE The yoke is a set of electromagnetic devices mounted on the CRT neck One device is for horizontal deflection of the electron beam the other is for vertical deflection Currents to control the...

Page 244: ...function of the position of the beam on the tube 8 7 2 Grid Bias This circuit generates CRT biasing values focus G4 cutoff G2 and brightness Gl These voltages are developed from the flyback transforme...

Page 245: ...horizontal deflection IC also provides the correct timing on its output pulse This allows the current ramp to continue after the damper diode stops conducting The width coil portion of the output stag...

Page 246: ...ts of an input and output stage The video signal is applied to an input push pull transistor network which is part of an encapsulated transistor array The input is provided from R5 the contrast thumbw...

Page 247: ...the clip lead of the anode discharge tool to the metal frame 3 Hold the tool by its insulated handle Using one hand carefully slide the tip of the tool under the plastic anode cap until it touches th...

Page 248: ...tor provides the horizontal and vertical deflection currents between the electronics board and the yoke assembly It is a four pin connector Pins one and four are used for vertical deflection pins two...

Page 249: ...e logic board SYSTEM BOX Figure 9 1 VIDEO LOGIC LOGIC __ L _ _ _ _ _ SYSTEM COMMUNICATION EIA PRINTER 20 rnA HOST PORT PORT PORT INTEGRAL OPTIONAL HOST COMMUNICATIONS MONITOR VR201 OR VR2411 MA Q054 8...

Page 250: ...t and fan components Power supply 1 PS1 DC power input connector Jl 5 V input circuit 12 V input circuits 12 V input circuit DC power Okay P S 1 ACINPUT AND FAN COMPONENTS FROM AC SOURCE LOGIC BOARD 5...

Page 251: ...l provides the voltage selection switch S2 provides the power on off switch that connects ac input to the PSI via the PSI LN connector a two pin quick disconnect jack F2 provides a 3 amp 250 Vac input...

Page 252: ...cification PS 3021383 0 0 The PSI electrical components Figure 9 5 are all located on a single PCB The PSI consist of the following circuits components Jl fan provides the connector for routing 12 VA...

Page 253: ...gulation consists of components responsible for ac input and regulation of isolation inrush current undervo1tage overvo1tage and high voltage transient conditions FROM ON OFF SWITCH 51 v SWITCH PIN CO...

Page 254: ...input regulation circuits Figure 9 7 is a circuit schematic of the dc output circuit and Figure 9 8 is a circuit schematic of the 5 1 V crowbar circuits Figure 9 9 shows the layout of the PSl componen...

Page 255: ...27 1 R23 F Zl SCRl 28 r r 18 f R24 22 J T ICl TO 5 1V CROWBAR r C25 T DC Output Circuits FROM T2 R16 1 L5 R17 D16 03 R18 R19 R20 f R21 C29 Ici R22 r l 5 1 V Crowbar Circuit 9 7 130 12VA 12VB 5 1V GRO...

Page 256: ...2 C6 B01 D Fl 25A 250V D g L O G B I C2 IC3 i R2 c J TMI c J IC4 R3 MA 0404 84 Figure 9 9 PSl Component Layout Table 9 1 lists the component values for the PSl components shows in Figures 9 6 9 7 and...

Page 257: ...ctifier Silicon diode Rectifier Schottky diode Bridge rectifier Fuse Regulator Regulator Choke Choke Choke Choke Choke NPN transistor NPN transistor PNP transistor 9 9 Description 0 1 uF 20 250 V 0 22...

Page 258: ...5 1 4 W R15 Carbon film 270 5 1 2 W R16 Metal oxide film 220 5 1 W R18 Carbon film 330 5 1 4 W R19 Carbon film 56 5 1 4 W R21 Carbon film 12 K 5 1 4 W R22 Carbon film 470 5 1 4 W R23 220 5 R24 Carbon...

Page 259: ...5 A peak thermisters cold 120 W max at full rated dc output load of 77 W 0 65 minimum output power to input power ratio Provides minimum of 5 millisecond hold up at 90 Vrms during power outage 150 Vac...

Page 260: ...m stability Overcurrent Overvo1 tage Nominal output Minimum load Maximum load Ripple and noise Total regulation Long term stability Overcurrent Value 5 1 V 4 A 6 5 A 50 mV peak to peak maximum see not...

Page 261: ...eraging 2 8 A or less with peak current of 3 A or less in any 10 second period or for a permanent short circuit short circuit current specified as 1 A maximum 12 V 0 03 A 0 3 A 50 mV peak to peak maxi...

Page 262: ...s from 5 1 V input Figure 9 11 shows the components circuit as well as the various developed by this circuit 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 PART OF PS1 12V 12V GROUND GROUND GROUND GROUND GRO...

Page 263: ...C42 O IUF r GB r i c 5 D 16 5 1V 17 18 C12 150UF 15V C9 560PF C1 C2 C7 C8 C19 C27 C14 C203 C207 C211 C219 C221 C231 C23B C239 C241 C244 C246 C253 C25B C259 C264 C221 19 Figure 9 11 t4 22UF I 5 V Input...

Page 264: ...ndication of dc input to the logic board Figure 9 14 shows that 5 V 12 V and 12 V potentials are applied as inputs to the dc power okay circuit When all three inputs are present Q2 is properly biased...

Page 265: ...host computer by using the terminal keyboard instead of a telephone set The modem has three operating modes accessible through the VT2413 terminal data mode talk mode and dialer mode SYSTEM BOX VIDEO...

Page 266: ...lowing features Direct connect telephone line interface Automatic answer Automatic originate dialing Test modes Speed control Keyboard control 10 1 2 Functional Description The integral modem connects...

Page 267: ...ce TLI The modem connects to the system logic board via a 3 pin stacK connector Figure 1 2 The telephone line and the telephone set connect to the TLI standard miniature telephone jacKs STANDOFFS Figu...

Page 268: ...lk data relay circuit Figure 10 4 connects the telephone line to either the handset or the modem The position of the talk data switch on the VT240 keyboard determines whether the handset or modem is c...

Page 269: ...OD MODEM 614 4 KHz CLOCK ffiTERCLK w f 0 Ol U Z l Ol w is J N N r r r f fl r c c fl 0 I Ol fl U 0 f G Ol f Ol Ol Ol 0 u u fl c Ol Ol f U U c f l J 0 Z f I STACK CONNECTOR TERM Figure 10 3 Block Diagra...

Page 270: ...g leads from the talk data relay to the protective circuit and is used to pulse dial the telephone system during the automatic dialing mode The signal OHD is passed from the terminal through the stack...

Page 271: ...following elements Figure 10 5 Hybrid amplifier High low filter Filter circuit Hybrid Amplifier The hybrid ampifier full duplex transmit channels AUDIO H 0 IC data AUDIO cL JA I COUPLER ANALOG OHD TE...

Page 272: ...range The receive data signal FILTER A has a carrier frequency in the 700 1700 Hz range The filter input switch routes the XMOD signal into the high bandpass filter and outputs the signal XMIT A to t...

Page 273: ...0 7 CCT HYBRID AMPLIFIER Figure 10 8 FILTER SWITCH X MOD ANS MODE MA 0418 84 Originate Mode MA 0419 84 Answer Mode FILTER SWITCH XMIT A X MOD ANS MODE MIX MA 0420 84 Test Mode 10 9 Artisan Technology...

Page 274: ...0 9 consists of the components Yl and E43 Yl generates a square wave clock signal with a frequency of 4 9152 MHz which is then divided into the following four subfrequency signals CLOCK A CLOCK B FILT...

Page 275: ...The circuit also detects the presence of a valid received data carrier and inputs the signal carrier detect CD back to the terminal The circuit generates the control signals CTS and DSR These signals...

Page 276: ...when the circuit voltage is more positive than 2 V with respect to signal ground and in the spacing condition when the voltage on the circuit is more negative than 2 V with respect to signal ground T...

Page 277: ...served Vol tage Coupler cut through Switch hook Off hook Test analog loop Remote digital loop Test mode indicator Da te term ready Clear to send Carrier detect Vol tage Source Active Level Term Modem...

Page 278: ...power 10 3 2 6 Carrier Detect CD Carrier detector on indicates that a data carrier is being received and has been received for at least 155 milliseconds This circuit differentiates a good data carrie...

Page 279: ...e or data mode to the modern 10 3 2 12 Data Available DA This signal is generated by the terminal to request a data transmission path cut through For pulse dialing the terminal disables the DA signal...

Page 280: ...opback Test RDL This interface signal causes the local 2l2A modem to put the remote 212A modem into a data loop Data from the terminal is then transmitted from the local modem to the remote modem and...

Page 281: ...kg 4 5 1bs terminals Height 29 2 em 11 5 in Width 34 9 em 13 75 in Depth 31 1 em 12 25 in Weight 6 4 kg 14 1b Adjustable Tilt 5 _25 He i g h t 3 2 4 em 1 2 75 in Width 38 0 em 15 in Depth 42 1 em 17...

Page 282: ...rs 7 X 9 dot matrix in 10 X 10 cell for 80 columns 5 X 9 dot matrix in 6 X 10 cell for 132 columns 3 35 mm X 2 0 mm for 80 columns 3 35 mm X 1 3 mm for 132 columns 202 mm X 115 mm 8 X 5 in ASCII DEC S...

Page 283: ...finish keys home row key height is 30mm 1 18 in above desk top 1 27 cm 0 5 in square 1 9 cm 0 75 in center to center single width keys 18 keys 36 keys firmware and software dr i ven 4 LED indicators h...

Page 284: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 285: ...OEM supplied character ROM NO SCROLL key 25 pin 50 60 Hz Display in English only Performs power up self test 7 pixels with 2 pixels between characters Off line mode disconnects modem B 1 VT240 Not pr...

Page 286: ...aud rate Selectable passive or active 20 rnA ESC 6 c B 2 VT240 Full duplex mode only and does not affect softwa re Optional transmit speed limitation of 150 characters per second Passive 20 rnA only C...

Page 287: ...hics Scales X and Y directions independently when mapping Uses integral divisions to map screen addressing range to physical pixels Ignores digits after a decimal point in screen addressing parameters...

Page 288: ...is slashed C 2 VT240 Images moved off screen are lost Scrolls image on 16 pixel boundaries horizontally and single pixel boundaries vertically When image is moved origin remains fixed at point define...

Page 289: ...tire screen Text can overlay graphics in same display region Erases text and graphics separately Changes only presentation of graphics image ESC 12 Pvt00 Pf Pvc C 3 VT240 Provides only for optional ex...

Page 290: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 291: ...NSMIT CHARACTER 01 1y STOP BITS PER TRANSMIT CHARACTER 11 2 STOP BITS PER TRANSMIT CHARACTER a a ODD PARITY GENERATION CHECK EVEN PARITY GENERATION CHECK PARITY DISABLED PARITY ENABLED BIT 2 3 00 5 BI...

Page 292: ...IT 2 BIT 1 BIT 0 Figure 0 2 o o o o o o o BIT VALUES DISABLE SEARCH FOR SYNC CHARACTERS SEARCH FOR SYNC NO EFFECT IN ASYNC INACTIVE INTE RNAL RESET NOT USED INACTIVE RESET ERROR FLAGS NORMAL OPERATION...

Page 293: ...T NO STOP CHARACTER DETECTED NO OVERRUN ERROR OE FLAG OE FLAG SET CPU FAILED TO READ Rx CHARACTER BEFORE NEW Rx CHARACTER NO PARITY ERROR PE FLAG PE FLAG SET PARITY ERROR SENSED NOT READY FOR Tx DATA...

Page 294: ...IT 5 0 CHARACTER ERROR MODE BLOCK ERROR MODE BIT 3 4 00 WITH PARITY 01 FORCE PARITY 10 NO PARITY 11 SPECIAL MODE BIT 2 0 EVEN PARITY ODD PARITY BIT 0 1 00 5 BITS PER CHARACTER 01 6 BITS PER CHARACTER...

Page 295: ...0 688 BIT STOP CHARACTER 0011 0 750 BIT STOP CHARACTER 0100 0 813 BIT STOP CHARACTER 0101 0 875 BIT STOP CHARACTER 0110 0 938 BIT STOP CHARACTER 0111 1 000 BIT STOP CHARACTER 1000 1 563 BIT STOP CHAR...

Page 296: ...ROR BIT VALUES NO BREAK DETECTED RECEIVE BREAK DETECTED NO ERROR FRAMING ERROR NO ERROR PARITY ERROR NO ERROR OVERRUN ERROR Tx NOT EMPTY Tx HOLDING AND SHIFT REGISTERS EMPTY Tx HOLDING REGISTER FULL T...

Page 297: ...9600 1100 38 4K 19 2K 1101 TIMER TIMER 1110 IP4 16X RxCA IP4 16X RxCA 1110 IP6 16X RxCBI IP6 16X RxCB 1110 IP3 16X TxCA IP3 16X TxCA 1110 IP5 16X TxCB IP5 16X TxCB 1111 IP4 1 X RxCA IP4 1 X RxCAI 111...

Page 298: ...S BIT 2 0 DISABLE Tx ENABLE Tx BIT 1 0 NO COMMAND TERMINATE Rx IMMEDIATELY BIT 0 0 DISABLE Rx ENABLE Rx MA 0236 84 Figure D 8 2681 DUART Command Register CR Channel A and B RDRA ADDRESS 172014 RD RDRB...

Page 299: ...CHANGE OF STATE DETECTED AT IPl CHANGE OF STATE DETECTED AT IPl NO CHANGE OF STATE DETECTED AT IPO CHANGE OF STATE DETECTED AT IPO CURRENT STATE OF IP3 CURRENT STATE OF IP2 CURRENT STATE OF IPl CURREN...

Page 300: ...R MODE TxCB AT 1X CLOCK OF CHANNEL B Tx COUNTER MODE CRYSTAL OR EXTERNAL CLOCK CLK DIVIDED BY 16 TIMER MODE EXTERNAL IIP2 SOURCE TIMER MODE EXTERNAL lP2 SOURCE DIVIDED BY 16 TIMER MODE CRYSTAL OR EXTE...

Page 301: ...SS 172026 WR 07 06 05 04 03 02 01 00 INPUT DELTA RxRDY TxRDY COUNTER DELTA RxRDY TxRDY PORT BREAK FFULL B READY BREAK FFUL CHANGE B B A A A RDA7 H ROAD H BIT VALUES BIT 7 0 INTERRUPT DISABLED INPUT PO...

Page 302: ...GURE OP4 AS COMPLIMENT OF Rx INTERRUPT RxRDY FFULL A COMPLIMENT OP3 FOR MOD SPD SEL L FALSE OUTPUT COMPLIMENT OP3 FOR MOD SPD SEL L TRUE OUTPUT COMPLIMENT OP2 FOR HOST DTR L FALSE OUTPUT COMPLIMENT OP...

Page 303: ...DATA AVAILABLE DATA AVAILABLE BIT 4 0 DOMESTIC MODEM TYPE BELL 103 EUROPEAN MODEM TYPE V 21 BIT 3 0 10 BITS PER CHARACTER 9 BITS PER CHARACTER BIT 2 0 TALK MODE DATA MODE BIT 0 1 00 EIA HOST PORT 01...

Page 304: ...LUES BIT 7 0 DIAL TONE DETECTED NO DIAL TONE DETECT BIT 6 0 OUTPUT OF MCWR BIT 6 SELECTS ORIGINATE MODE OUTPUT OF MCWR BIT 6 SELECTS ANSWER MODE BIT 5 0 OUTPUT OF MCWR BIT 5 SELECTS BELL 103 OR V 21 O...

Page 305: ...OC Status Register ADDRESS 174600 WR CPU ADDRESS COH WR CP 07 06 05 04 03 02 01 00 ERA SVP SGDC SLU SVEC EVOM SM1 SMO VDB7H 4 VDBOH BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 0 1 00 01 10 11...

Page 306: ...ESS BOH WR CP 07 06 05 04 03 02 01 00 M1 MO IF1 IFO IB1 IBO SP PS VDB7 H 4 VDBO H BIT VALUES BIT 6 7 00 REPLACE WRITING 10 OVERLAY WRITING 01 NOT USED 11 COMPLIMENT WRITING BIT 5 0 1 FOREGROUND INTENS...

Page 307: ...3 02 01 00 WE 7 LI WEO L LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 x x x x x x x X M1 MO IF1 IFO IB1 IBO SP PS M1 1 H I I JH IF1 H IB1 H MO H IFO H IBO H PS H NOTES 1 GDC COMMANDS USE CURS COMMAND T...

Page 308: ...ATCH 07 06 05 04 03 02 01 00 IWETL IWEOl LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 ISET APPROPRIATELY IPS IMl H IIFl H IIBl H ISP H IMO H liFO H IIBO H IPS H NOTES 1 GDC COMMANDS USE CURS COMMAND FO...

Page 309: ...EL SD H NOT USED WRITE MASK LATCH 07 06 05 04 03 02 01 00 X X X X X X X X 4 _ WEOL WE T LI LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 SET APPROPRIATELY PS M1 H IF1 H IB1 H SP H MO H IFO H IBO H PS H...

Page 310: ...04 03 02 01 00 a a a a a a a a WE T LI WEO LI LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 a 1 a a a a a a M11 Mal IF11 IFOI IB11 IBOI SPI PSI M HI I I JHI IF1 HI IB1 HI MO HI IFO HI IBO HI PS HI NOTES...

Page 311: ...6 05 04 03 02 01 a a a 0 a a a WE T L LOGIC UNIT REGISTER 07 a M1 M H 06 05 04 03 02 01 DESI ED 0 x X INTENSITY a MO IF1 IFO IB1 I IBO SP IJ H I JH IB1 H MO H IFO H IBO H NOTES 1 SET VECTOR PATTERN RE...

Page 312: ...04 03 02 01 00 a a 0 a a 0 0 0 WE T L WEO L LOGIC UNIT REGISTER 07 06 05 04 03 02 01 00 a a X X DESIRED a X INTENSITY M1 MO IIF1 liFO IIB1 I IBO SP PS M H I IIB1 H JH lF1 H MO H IFO H IBO H PS H NOTE...

Page 313: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 314: ...I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 315: ...2 1 3 1 c4 1 5 1 d Clearness of Language 1 2 1 3 4 c5 e Helpfulness of Index Table of Contents 1 0 e2 o e3 o c4 o e5 J f Consistency in Presenting Information 1 c2 3 c 4 c5_ g Logical Organization 1...

Page 316: ...LL BE PAID BY ADDRESSEE DIGITAL EQUIPMENT CORPORATION Educational Services Quality Assurance 12 Crosby Drive BUO E08 Bedford MA 01730 FOLD HERE II No Postage Necessary if Mailed in the United States A...

Page 317: ...Digital Equipment Corporation Maynard MA 01754 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 318: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

Search results

Summary of Contents for 93959-1

Reviews:

Brands by name

Popular brands

Digital Equipment 93959-1, Technical Manual

Search results

Summary of Contents for 93959-1

Reviews:

Brands by name

Popular brands