Digilent ZYBO Reference Manual Download Page 3

ZYBO™ FPGA Board Reference Manual 

 

 

Copyright Digilent, Inc. All rights reserved. 

Other product and company names mentioned may be trademarks of their respective owners.

 

Page 

3

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26

 

 

 

 

 

 

Callout 

Component Description 

Callout 

Component Description 

1

 

Power Switch 

15

 

Processor Reset Pushbutton 

2

 

Power Select Jumper and battery header 

16

 

Logic configuration reset Pushbutton 

3

 

Shared UART/JTAG USB port 

17

 

Audio Codec Connectors 

4

 

MIO LED 

18

 

Logic Configuration Done LED 

5

 

MIO Pushbuttons (2) 

19

 

Board Power Good LED 

6

 

MIO Pmod 

20

 

JTAG Port for optional external cable 

7

 

USB OTG Connectors 

21

 

Programming Mode Jumper 

Logic LEDs (4) 

22 

Independent JTAG Mode Enable Jumper  

Logic Slide switches (4) 

23 

PLL Bypass Jumper  

10 

USB OTG Host/Device Select Jumpers 

24 

VGA connector 

11 

Standard Pmod 

25 

microSD connector (Reverse side) 

12 

High-speed Pmods (3) 

26 

HDMI Sink/Source Connector 

13 

Logic Pushbuttons (4) 

27 

Ethernet RJ45 Connector 

14 

XADC Pmod 

28 

Power Jack 

 

Table 1. ZYBO Device Diagram. 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

Summary of Contents for ZYBO

Page 1: ...he rich set of multimedia and connectivity peripherals available on the ZYBO the Zynq Z 7010 can host a whole system design The on board memories video and audio I O dual role USB Ethernet and SD slot...

Page 2: ...ed The ZYBO is compatible with Xilinx s new high performance Vivado Design Suite as well as the ISE EDK toolset These toolsets meld FPGA logic design with embedded ARM software development into an eas...

Page 3: ...O LED 18 Logic Configuration Done LED 5 MIO Pushbuttons 2 19 Board Power Good LED 6 MIO Pmod 20 JTAG Port for optional external cable 7 USB OTG Connectors 21 Programming Mode Jumper 8 Logic LEDs 4 22...

Page 4: ...is limit varies a lot between manufacturers and depends on many factors When in current limit once the voltage rails dip below their nominal value the Zynq is reset by the Power on Reset signal and po...

Page 5: ...ply rails are daisy chained to follow the Xilinx recommended start up sequence Flicking the power switch SW4 will enable the 1 0V rail which enables the 1 8V digital supply rail which in turn enables...

Page 6: ...itecture AMBA Interconnect DDR3 Memory controller and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins called MultiplexedI O or MIO pins Peripheral control...

Page 7: ...on refer to the Zynq Technical Reference Manual available at www xilinx com Figure 3 depicts the external components connected to the MIO pins of the ZYBO The Zynq Board Definition File found on the D...

Page 8: ...IO 501 1 8V Peripherals Pin ENET 0 USB 0 SDIO 0 UART 1 GPIO 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL 28 DATA4 29 DIR 30 STP 31 NXT 32 DATA0 33...

Page 9: ...of non volatile memory specified by the mode register to the 256 KB of internal RAM within the APU called On Chip Memory or OCM The FSBL must be wrapped up in a Zynq Boot Image in order for the BootR...

Page 10: ...lect it using JP7 6 Place a single jumper on JP5 shorting the two leftmost pins labeled SD 7 Turn the board on The board will now boot the image on the microSD card 3 2 QSPI Boot Mode The ZYBO has an...

Page 11: ...oting the Zynq 7000 AP SoC The relevant device attributes are 128Mbit x1 x2 and x4 support Speeds up to 104 MHz supporting Zynq configuration rates 100 MHz In Quad SPI mode this translates to 400Mbs P...

Page 12: ...ss variations and thermal drift Optimum starting values for the training process are the board delays propagation delays for certain memory signals Board delays are specified for each of the byte grou...

Page 13: ...ith a single Micro USB cable 7 MicroSD Slot The ZYBO provides a microSD slot J4 for non volatile external memory storage as well as booting the Zynq The slot is wired to Bank 1 501 MIO 40 47 including...

Page 14: ...ect to a USB host device and JP1 should not be shorted When acting as an embedded host the USB A connector J10 should be used to connect to a USB peripheral device and JP1 should be shorted The ZYBO s...

Page 15: ..._CLK ACT LED LD7 LINK LED LD6 LED0 PHY_AD0 LED1 PHY_AD1 Figure 7 Ethernet PHY signals Two status indicator LEDs are on board near the RJ 45 connector that indicate traffic LD7 and valid link state LD6...

Page 16: ...sed from the PS over EMIO as well The device address of the EEPROM is 1010000b For more information on using the Gigabit Ethernet MAC refer to the Xilinx Zynq TRM ug585 10 HDMI Source Sink Port An inp...

Page 17: ...d uses 18 programmable logic pins to create an analog VGA output port This translates to 16 bit color depth and two standard sync signals HS Horizontal Sync and VS Vertical Sync The digital to analog...

Page 18: ...lection control R G B signals to guns Cathode ray tube Cathode ray VGA cable Figure 9 Color CRT display Electron beams emanate from electron guns which are finely pointed heated cathodes placed in clo...

Page 19: ...the cathode makes over the display area and a number of columns that corresponds to an area on each row that is assigned to one picture element or pixel Typical displays use from 240 to 1200 rows and...

Page 20: ...tical Sync 32 us 25 6 us 3 84 us 640 ns 1 92 us 800 640 96 16 48 Clks Horiz Sync Time Figure 11 Signal timings for a 640 pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh A...

Page 21: ...nal reference clock can be used as an input to the MMCMs and PLLs For a full description of the capabilities of the Zynq PL clocking resources refer to the 7 Series FPGAs Clocking Resources User Guide...

Page 22: ...and USB and Ethernet port status The LED and two pushbuttons attached directly to the PS are accessed using the Zynq GPIO controller This core is described in full in Chapter 14 of the Zynq Technical...

Page 23: ...ire a master clock of 12 288 Mhz resulting in a 48 kHz sampling rate For other frequencies and their respective configuration parameters consult the SSM2603 datasheet The codec has two modes master an...

Page 24: ...es DONE to be de asserted The PL will remain unconfigured until it is reprogrammed by the processor or via JTAG 15 3 Processor Subsystem Reset The external system reset labeled PS_SRST BTN7 resets the...

Page 25: ...the user accidently drives a signal that is supposed to be used as an input The downside to this added protection is that these resistors can limit the maximum switching speed of the data signals If...

Page 26: ...on on using the XADC core refer to the Xilinx document titled 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter It is also possible to access the XA...

Page 27: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 279P KIT 410 279...

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