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JTAG-HS2 Reference Manual 

 

 

Doc: 502-249 

 

page 4 of 5 

 
  When the JTAG-HS2 first receives power the three-state buffers attached to the TMS, TDI, and TCK 
signals move into a high-impedance state. They remain in the high-impedance state until an 
application enables the HS2’s JTAG or SPI port. Once these ports activate, the buffers actively drive 
the TMS, TDI, and TCK signals until the port is disabled. 
 
  The IEEE 1149.7-2009 specification requires any device that functions as a Debug and Test System 
(DTS) to provide a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the 
JTAG-HS2 features weak pull-ups (100K ohm) on the TMS, TDI, TDO, and TCK signals. While not 
strictly required, the pull-ups on the TDI and TCK signals ensure that neither signal floats while 
another source is not actively driving them. 
 
  The JTAG-HS2 can interface scan chains that consist of one or more IEEE 1149-7 compatible 
Target Systems (TS). The devices in these chains communicate using the TMS, TDI, TDO, and TCK 
signals or they may communicate using only the TMS and TCK signals. Communication using only 
the TMS and TCK signals requires both the HS2 and TS to drive the TMS pin. The current scan 
format, bit period, and the level of the TCK pin determine which device is allowed to drive the TMS 
pin.  
   
  A drive conflict may occur when the HS2 and TS disagree on the current scan format setting or bit 
period. In the event that a drive conflict occurs, the 100 ohm resistor between the TMS buffer and 
output pin will limit the maximum current to 50 mA to prevent any damage from occurring to the 
JTAG-HS2. The drive conflict may be resolved by having the JTAG-HS2 perform a reset escape, 
which will reset the scan format of the TS to JScan0/JScan1. If the TMS pin of the TS is not capable 
of sourcing or sinking VDD (VREF) ÷ 100 amps of current then an additional resistor should be placed 
in series with the TMS pin of the TS to further limit current flow. 
 
  In most cases a drive conflict can be avoided by having applications that use the HS2 communicate 
with the TS in two wire mode.  Use the applications to reconfigure the TS to use the JScan0, JScan1, 
JScan2, or JScan3 scan format prior to disabling the HS2’s JTAG port. 
 

 
Absolute Maximum Ratings

 

 

Symbol 

Parameter 

Condition 

Min 

Max 

Unit 

VDD (VREF) 

I/O reference/supply voltage 

 

-0.5 

VIO 

Signal Voltage 

 

-0.5 

I

IK

,I

OK

  

TMS, TCK, TDI, TDO 

DC Input/Output Diode Current 

VIO < -0.5V 

 

-50 

mA 

VIO > 6V 

+20 

I

OUT

 

DC Output Current 

 

 

±50 

mA 

T

STG

 

Storage Temperature 

 

-20 

+120 

ºC 

ESD 

Human Body Model JESD22-A114 

 

4000 

Charge Device Model JESD22-C101 

 

2000 

 
 
 

Summary of Contents for JTAG-HS2

Page 1: ... up to 30MBit sec See figure 1 To function correctly the HS2 s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA The JTAG bus can be shared with other devices as systems hold JTAG signals at high impedance except when actively driven during programming The HS2 comes included with a standard Type A to Micro USB cable that attaches to the end of the module opposit...

Page 2: ... Digilent s website This Adept software includes a full featured programming environment and a set of public application programming interfaces API that allow user applications to directly drive the JTAG chain With the Adept SDK users can create custom applications that will drive JTAG ports on virtually any device Users may utilize the API s provided by the SDK to create applications that can dri...

Page 3: ...OC Target System 0 Target System 1 Target System N TMSC TDIC TCKC TDOC TMSC TDIC TCKC TDOC TMS TDI TCK TDO Host JTAG HS2 DTS The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP controller using the MScan OScan0 and OScan1 scan formats Design Notes The JTAG HS2 uses high speed three state buffers to drive the TMS TDI and TCK signals These buffers a...

Page 4: ... format bit period and the level of the TCK pin determine which device is allowed to drive the TMS pin A drive conflict may occur when the HS2 and TS disagree on the current scan format setting or bit period In the event that a drive conflict occurs the 100 ohm resistor between the TMS buffer and output pin will limit the maximum current to 50 mA to prevent any damage from occurring to the JTAG HS...

Page 5: ... TDO Input High Voltage VIH 1 62 5 5 Volts Input Low Voltage VIL 0 0 65 Volts TMS TCK TDI Output High VOH 0 85 x Vdd 0 95 x Vdd Vdd Volts Output Low VOL 0 0 05 x Vdd 0 15 x Vdd Volts AC Operating Characteristics The JTAG HS2 JTAG signals and SPI operate according to the timing diagram in Figure 7 The HS2 supports TCK frequencies from 30 MHz to 8 KHz at integer divisions of 30MHz from 1 to 3750 Com...

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