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Atlys Reference Manual

Doc: 502-178

page 16 of 19

contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and
the clock period is 20 to 30KHz.

The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a
positive number in the X field, and moving to the left generates a negative number. Likewise, moving
the mouse up generates a positive number in the Y field, and moving down represents a negative
number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number).
The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the
number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow
indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit
transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and
Right button presses (a ‘1’ indicates the button is being pressed).

Basic I/O

The Atlys board includes six pushbuttons, eight slide switches, and eight LEDs for basic digital input
and output. One pushbutton has a red plunger and is labeled "reset" on the PCB silkscreen – this
button is no different than the other five, but it can be used as a reset input to processor systems. The
buttons and slide switches are connected to the FPGA via series resistors to prevent damage from
inadvertent short circuits. The high efficiency LED anodes are connected to the FPGA via 390-ohm
resistors, and they will brightly illuminate with about 1mA of current when a logic high voltage is
applied to their respective I/O pin.

Pushbuttons

Slide Switches

LEDs

BTNU: N4

SW0: A10

LD0: U18

BTNC: F5

SW1: D14

LD1: M14

BTNR: F6

SW2: C14

LD2: N14

BTNL: P4

SW3: P15

LD3: L14

BTND: P3

SW4: P12

LD4: M13

BRST: T15 SW5: R5

LD5: D4

SW6: T5

LD6: P16

SW7: E4

LD7: N12

Mouse Data Format

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Summary of Contents for Atlys

Page 1: ...es each containing four 6 input LUTs and eight flip flops 2 1Mbits of fast block RAM four clock tiles eight DCMs four PLLs six phased locked loops 58 DSP slices 500MHz clock speeds The Atlys board includes Digilent s newest Adept USB2 system which offers device programming real time power supply monitoring automated board tests virtual I O and simplified user data transfer facilities A comprehensi...

Page 2: ...it remains valid until it is erased by removing power or asserting the PROG_B input or until it is overwritten by a new configuration file FPGA configuration files transferred via the JTAG port use the bin or svf file types files transferred from a USB stick use the bit file type and SPI programming files can use bit bin or mcs types The ISE WebPack or EDK software from Xilinx can create bit svf b...

Page 3: ...ower supply monitor without interference Adept System Digilent s Adept high speed USB2 system can be used to program the FPGA and ROM run automated board tests monitor the four main board power supplies add PC based virtual I O devices like buttons switches and LEDs to FPGA designs and exchange register based and file based data with the FPGA Adept automatically recognizes the Atlys board and pres...

Page 4: ...the startup clock must be set to CCLK The Read Write tools allow data to be exchanged between files on the host PC and specified address ranges in Flash Test Interface The test interface provides a quick and easy way to verify many of the board s hardware circuits and interfaces These are divided into two major categories on board memory DDR2 and Flash and peripherals In both cases the FPGA is con...

Page 5: ...d in a buffer that can be saved to a file for later analysis The Save Buffer and Clear Buffer are used to save and clear the historical data in the buffer Register I O The register I O tab requires that a corresponding IP block available in a reference design on the Digilent website is included and active in the FPGA This IP block provides an EPP style interface where an 8 bit address selects a re...

Page 6: ...board DDR2 and Flash memories A reference design demonstrating the required IP is available on the Digilent website I O Expand The I O Expand tab works with an IP block in the FPGA to provide additional simple I O beyond the physical devices found on the Atlys board Virtual I O devices include a 24 LED light bar 16 slide switches 16 push buttons 8 discrete LEDs a 32 bit register that can be sent t...

Page 7: ...curate to within 1 these measured values can be viewed on a PC using the power meter that is a part of the Adept software Power Jack Battery Connector Power Select Jumper JP13 VU 1 8V 1 2V 2 5V 3 3V IC16 IC15 IC16 IC15 EN Power Switch Vswt IC17 EN 0 9V 01Ω LTC2481 To Digilent Adept USB I2C Bus IC14 To Expansion Connectors HDMI USB PG PG PG PG EN EN EN Power On LED LD15 LT3501 3A Regulator LTC3546 ...

Page 8: ... Spartan 6 FGPA The DDR2 device a Micron MT47H64M16 25E or equivalent provides a 16 bit bus and 64M locations The Atlys board has been tested for DDR2 operation at up to an 800MHz data rate The DDR2 interface follows the pinout and routing guidelines specified in the Xilinx Memory Interface Generator MIG User Guide The interface supports SSTL18 signaling and all address data clocks and control sig...

Page 9: ...sed to demonstrate and check all of the devices and circuits on the Atlys board Ethernet PHY The Atlys board includes a Marvell Alaska Tri mode PHY the 88E1111 paired with a Halo HFJ11 1G01E RJ 45 connector Both MII and GMII interface modes are supported at 10 100 1000 Mb s Default settings used at power on or reset are MII GMII mode to copper interface Auto Negotiation Enabled advertising all spe...

Page 10: ... A connectors and the unbuffered port uses a type D connector loaded on the bottom side of the PCB immediately under the Pmod connector the type D connector is much smaller than the type A The data signals on the unbuffered port are shared with a Pmod connector This limits signal bandwidth somewhat the shared connector may not be able to produce or receive the highest frequency video signals parti...

Page 11: ...3 D2 A12 A8 J18 3 D2 N5 4 D1 B11 C7 L17 4 D2_S GND 5 D1_S GND GND GND 5 D2 P6 6 D1 A11 A7 L18 6 D1 T4 7 D0 G9 D8 K17 7 D1_S GND 8 D0_S GND GND GND 8 D1 V4 9 D0 F9 C8 K18 9 D0 R3 10 Clk D11 B6 H17 10 D0_S GND 11 Clk_S GND GND GND 11 D0 T3 12 Clk C11 A6 H18 12 Clk T9 13 CEC NC 0K to Gnd NC 13 Clk_S GND 14 RES NC NC NC 14 Clk V9 15 SCL C13 D9 M16 15 CEC VCCB2 16 SDA A13 C9 M18 16 Gnd GND 17 Gnd GND G...

Page 12: ...dec is compliant to the AC 97 v2 1 Intel standard and is connected as a Primary Codec ID1 0 ID0 0 The table below shows the AC 97 codec control and data signals All signals are LVCMOS33 Signal Name FPGA Pin Pin Function AUD BIT CLK AH17 12 288MHZ serial clock output driven at one half the frequency of the 24 576MHz crystal input XTL_IN AUD SDI AE18 Serial Data In to the FPGA from the codec SDI dat...

Page 13: ...ur phases of the input frequency 0º 90º 180º and 270º a divided clock that can be the input clock divided by any integer from 2 to 16 or 1 5 2 5 3 5 7 5 and two antiphase clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any integer from 1 to 32 PLLs use VCOs that can be programmed to generate frequencies in the 400MHz to 1080MHz range by setting three ...

Page 14: ...ed to the USB host interface Mice and keyboards that use the PS 2 protocol use a two wire serial bus clock and data to communicate with a host device Both use 11 bit words that include a start stop and odd parity bit but the data packets are organized differently and the keyboard interface allows bi directional data transfers so the host device can illuminate state LEDs on the keyboard Bus timings...

Page 15: ...st only when both the data and clock lines are high or idle Since the host is the bus master the keyboard must check to see whether the host is sending data before driving the bus To facilitate this the clock line is used as a clear to send signal If the host pulls the clock line low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words...

Page 16: ...the 33 bit transmissions are repeated every 50ms or so The L and R fields in the status byte indicate Left and Right button presses a 1 indicates the button is being pressed Basic I O The Atlys board includes six pushbuttons eight slide switches and eight LEDs for basic digital input and output One pushbutton has a red plunger and is labeled reset on the PCB silkscreen this button is no different ...

Page 17: ...available from Digilent and from distributors All FPGA pins routed to the VHDC connector are located in FPGA I O bank 2 The bank 2 I O power supply pins and the VHDC connector s four Vcc pins are connected to an exclusive sub plane in the PCB and this sub plane can be connected to 2 5V or 3 3V depending on the position of jumper JP12 This arrangement allows peripheral boards and the FPGA to share ...

Page 18: ... and eight logic signals VCC and Ground pins can deliver up to 1A of current Jumper JP12 selects the Pmod Vcc voltage 3 3V or 2 5V in addition to selecting the VHDC voltage Pmod data signals are not matched pairs and they are routed using best available tracks without impedance control or delay matching On the Atlys board the eight Pmod signals are shared with eight data signals routed to an HDMI ...

Page 19: ...are connected to the user LEDs The user buttons BTNU BTND BTNR BTNL BTNC and RESET cause varying sine wave frequencies to be driven on the LINE OUT and HP OUT audio ports If the self test is not resident in the SPI Flash ROM it can be programmed into the FPGA or reloaded into the ROM using the Adept programming software All Atlys boards are 100 tested during the manufacturing process If any device...

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