Digilent Arty Z7 Reference Manual Download Page 5

 

Arty Z7 Reference Manual  

Transfer Multisort Elektronik  / tme.eu  

Software Support 

The Arty Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This 
toolset melds FPGA logic design and embedded ARM software development into an easy to 
use, intuitive design flow. It can be used for designing systems of any complexity, from a 
complete operating system running multiple server applications in tandem, down to a simple 
bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a 
standalone FPGA for those not interested in using the processor in their design. As of Vivado 
release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to 
use for all WebPACK targets, which includes the Arty Z7. The Logic Analyzer assists with 
debugging logic, and the HLS tool allows you to compile C code directly into HDL.  

Zynq platforms are well-suited to be embedded Linux targets, and Arty Z7 is no exception. To 
help you get started, Digilent provides a Petalinux project that will get you up and running 
with a Linux system quickly. For more information, see the 

Arty Z7 Resource Center

.  

The Arty Z7 can also be used in Xilinx's SDSoC environment, which allows you to design 
FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. 
For more information on SDSoC, see the 

Xilinx SDSoC Site

. Digilent will be releasing a 

Video capable platform with Linux support in time for the SDSoC 2017.1 release. Note that 
due to the smaller FPGA in the Arty Z7-10, only very basic video processing demos are 
included with that platform. Digilent recommends the Arty Z7-20 for those interested in video 
processing.  

Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can 
also choose to use the Arty Z7 in that toolset. Digilent does not have many materials to 
support this, but you can always ask for help on the 

Digilent Forum

.  

 
 

1 Power Supplies 

The Arty Z7 can be powered from the Digilent USB-JTAG-UART port (J14) or from some 
other type of power source such as a battery or external power supply. Jumper JP5 (near the 
power switch) determines which power source is used.  

A USB 2.0 port can deliver maximum 0.5A of current according to the specifications. This 
should provide enough power for lower complexity designs. More demanding applications, 
including any that drive multiple peripheral boards or other USB devices, might require more 
power than the USB port can provide. In this case, power consumption will increase until it’s 
limited by the USB host. This limit varies a lot between manufacturers of host computers and 
depends on many factors. When in current limit, once the voltage rails dip below their 
nominal value, the Zynq is reset by the Power-on Reset signal and power consumption returns 
to its idle value. Also, some applications may need to run without being connected to a PC’s 
USB port. In these instances an external power supply or battery can be used.  

Summary of Contents for Arty Z7

Page 1: ...a unique set of software defined peripherals and controllers tailored by you for the target application The Vivado Petalinux and SDSoC toolsets each provide an approachable path between defining your...

Page 2: ...Arty Z7 Reference Manual Transfer Multisort Elektronik tme eu 2...

Page 3: ...sh with factory programmed 48 bit globally unique EUI 48 64 compatible identifier o microSD slot Power o Powered from USB or any 7V 15V external power source USB and Ethernet o Gigabit Ethernet PHY o...

Page 4: ...s Look up Tables LUTs 17 600 53 200 Flip Flops 35 200 106 400 Block RAM 270 KB 630 KB Clock Management Tiles 2 4 Available Shield I O 26 49 On the Arty Z7 10 the inner row of the digital shield IO26 I...

Page 5: ...t will be releasing a Video capable platform with Linux support in time for the SDSoC 2017 1 release Note that due to the smaller FPGA in the Arty Z7 10 only very basic video processing demos are incl...

Page 6: ...wer input Table 1 1 provides additional information typical currents depend strongly on Zynq configuration and the values provided are typical of medium size speed designs The Arty Z7 does not have a...

Page 7: ...rious peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins called Multiplexed I O or MIO pins Peripheral controllers that do not have their inputs and outputs connecte...

Page 8: ...The Zynq Presets File found on the Arty Z7 Resource Center can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals MIO 500 3 3 V Peripherals Pin ENET 0...

Page 9: ...A devices APSoC devices such as the Zynq 7020 are designed around the processor which acts as a master to the programmable logic fabric and all other on chip peripherals in the processing system This...

Page 10: ...s hand off execution to the FSBL in OCM Stage 1 During this stage the FSBL first finishes configuring the PS components such as the DDR memory controller Then if a bitstream is present in the Zynq Boo...

Page 11: ...shorting the two top pins labeled SD 7 Turn the board on The board will now boot the image on the microSD card 3 2 Quad SPI Boot Mode The Arty Z7 has an onboard 16MB Quad SPI Flash that the Zynq can...

Page 12: ...ze the PS subsystem as well as configure the PL subsystem The relevant device attributes are 16 MB x1 x2 and x4 support Bus speeds up to 104 MHz supporting Zynq configuration rates 100 MHz In Quad SPI...

Page 13: ...correct parameters For best DDR3 performance DRAM training is enabled for write leveling read gate and read data eye options in the PS Configuration Tool in Xilinx tools Training is done dynamically b...

Page 14: ...be programmed communicated with via UART and powered from a computer attached with a single Micro USB cable The DTR signal from the UART controller on the FT2232HQ is connected to MIO12 of the Zynq d...

Page 15: ...p USB3320 USB 2 0 Transceiver Chip with an 8 bit ULPI interface is used as the PHY The PHY features a complete HS USB Physical Front End supporting speeds of up to 480Mbs The PHY is connected to MIO B...

Page 16: ...urpose then the Arty Z7 should be powered via a battery or wall adapter capable of providing more power such as the one included in the Arty Z7 accessory kit 9 Ethernet PHY The Arty Z7 uses a Realtek...

Page 17: ...he MDIO bus is available for management The RTL8211E VL is assigned the 5 bit address 00001 on the MDIO bus With simple register read and write commands status information can be read out or configura...

Page 18: ...V signal capable of delivering up to 50mA and one reserved RES pin All non power signals are wired to the Zynq PL with the exception of RES Pin Signal J11 source J10 sink Description FPGA pin Descript...

Page 19: ...ng a common CEC wire Refer to the CEC addendum of HDMI 1 3 or later specifications for more information 11 Clock Sources The Arty Z7 provides a 50 MHz clock to the Zynq PS_CLK input which is used to g...

Page 20: ...ttons and 4 individual LEDs as shown in Figure 12 1 The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits a short circ...

Page 21: ...steady logic 1 will result in the LED being illuminated at an uncomfortably bright level You can avoid this by ensuring that none of the tri color signals are driven with more than a 50 duty cycle Us...

Page 22: ...UD_SD is used to mute the audio output It is connected to Zynq PL pin T17 To use the audio output this signal must be driven to logic high The frequency response of SK Butterworth Low Pass Filter is s...

Page 23: ...tegrated to define an analog voltage The low pass filter 3dB frequency should be an order of magnitude lower than the PWM frequency so that signal energy at the PWM frequency is filtered from the sign...

Page 24: ..._RST signal to toggle in order to trigger a reset on any attached shields 15 Pmod Ports Pmod ports are 2 6 right angle 100 mil spaced female connectors that mate with standard 2 6 pin headers Each 12...

Page 25: ...Pmods have 0 ohm shunts instead of protection resistors the operator must take precaution to ensure that they do not cause any shorts 16 Arduino chipKIT Shield Connector The Arty Z7 can be connected t...

Page 26: ...Shield Digital I O SCL I2C Clock See Section titled Shield Digital I O SDA I2C Data See Section titled Shield Digital I O SCLK SPI Clock See Section titled Shield Digital I O MOSI SPI Data out See Se...

Page 27: ...e external power supply connector J18 Table 16 1 Shield Pin Descriptions 16 1 Shield Digital I O The pins connected directly to the Zynq PL can be used as general purpose inputs or outputs These pins...

Page 28: ...16 2 1 Single Ended Analog Inputs The pins labeled A6 A11 are connected directly to 3 pairs of analog capable pins on the Zynq PL via an anti aliasing filter This circuit is shown in Figure 16 2 2 The...

Page 29: ...ign via the Dynamic Reconfiguration Port DRP The DRP also provides access to voltage monitors that are present on each of the FPGA s power rails and a temperature sensor that is internal to the FPGA F...

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