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ZIRCON-MM

8-Bit Resolution Analog & Digital I/O

PC/104 Module

User Manual V2.11



Diamond Systems Corporation

8430-D Central Ave.

Newark, CA 94560

Tel (510) 456-7800

Fax (510) 45-7878

[email protected]

www.diamondsystems.com

Summary of Contents for ZIRCON-MM

Page 1: ...lution Analog Digital I O PC 104 Module User Manual V2 11 Copyright 2002 Diamond Systems Corporation 8430 D Central Ave Newark CA 94560 Tel 510 456 7800 Fax 510 45 7878 techinfo diamondsystems com www...

Page 2: ...der Pinout 4 3 Base Address Configuration 5 4 Interrupt Configuration 5 5 Analog I O Configuration 6 6 Zircon MM Board Drawing 8 7 Register Map 9 8 Register definitions 10 9 Digital I O Operation 13 1...

Page 3: ...by an on board 4MHz clock oscillator The third counter timer is available at the I O header All I O lines are TTL and CMOS compatible ZIRCON MM is an 8 bit bus module and conforms to the physical and...

Page 4: ...39 40 C0 B7 41 42 B6 B5 43 44 B4 B3 45 46 B2 B1 47 48 B0 5 Digital 49 50 Digital Gnd Definitions Analog In 7 0 Analog input channels range depends on configuration Analog Out Analog output channel ran...

Page 5: ...ith header J6 located in the lower center of the board One position is used for the PC 104 1K pulldown resistor to enable interrupt sharing This resistor should be connected if interrupts are used Onl...

Page 6: ...gative and positive input voltages and the analog output can create both negative and positive voltages The analog input range on this model can be set to 0 1 25V 0 2 5V or 0 5V in unipolar mode and 1...

Page 7: ...further modified by the setting of D above B Bipolar range On ZMM DX installing a jumper in this position will configure the analog inputs and output for bipolar ranges depending on the position of D...

Page 8: ...CON MM User Manual v2 11 2002 Diamond Systems Corporation P 8 6 ZIRCON MM BOARD DRAWING This drawing will help to locate various key features on the board as described in the configuration sections ab...

Page 9: ...gital I O port B Digital I O port B 10 Digital I O port C Digital I O port C 11 Digital I O configuration register 12 Counter timer 0 data 82C54 Counter timer 0 data 13 Counter timer 1 data Counter ti...

Page 10: ...ed output voltage to the corresponding input output code Base 0 or 1 A D Register Read only Both these addresses map to the same physical register on the board Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3...

Page 11: ...unter 2 output is not used Ch2 Ch0 A D channel select Ch2 Ch1 Ch0 Input channel 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Base 4 or 5 Status register Read only Both these address...

Page 12: ...ports as desired Bit No 7 6 5 4 3 2 1 0 Name 1 ModeC ModeA DirA DirCH ModeB DirB DirCL Definitions 1 Bit 7 must be set to 1 to indicate port mode set operation DirA Direction control for bits A7 A0 0...

Page 13: ...output and each half of port C can be independently configured for input or output Output data is latched in the chip but input data is not latched When reading a port that is in input mode the curren...

Page 14: ...mmed 16 bit value the divisor The formula for determining the output frequency of this counter pair is Output frequency 4Mz counter 2 divisor x counter 1 divisor The minimum divisor value for each cou...

Page 15: ...g I O is limited to positive voltages 0 2 5V or 0 1 25V ranges On ZMM DX the analog circuitry is powered by an on board DC DC converter that provides dedicated 5 5 supplies to the board Using these su...

Page 16: ...5mV Input voltage 5V x A D code 256 ZMM DX only 1 25V 9 8mV Input voltage 2 5V x A D code 256 ZMM DX only 0 5V 19 5mV Input voltage 5V x A D code 256 ZMM DX only 0 2 5V 9 8mV Input voltage 2 5V x A D...

Page 17: ...ettling time 4 s max to 1 2 LSB Offset error 2 LSB max Full scale error 2 LSB max Output current 1 25mA max Digital I O No of lines 24 using 82C55 chip Compatibility TTL CMOS Pull up resistors 10K on...

Page 18: ...compatible with the Harris 80C86 80C88 and 80C286 CMOS microprocessors along with many other industry standard processors Six programmable timer modes allow the 82C54 to be used as an event counter el...

Page 19: ...28 Lead CLCC J28 A CM82C54 CM82C54 10 CM82C54 12 0oC to 70oC 24 Lead SOIC M24 3 Pin Description SYMBOL DIP PIN NUMBER TYPE DEFINITION D7 D0 1 8 I O DATA Bi directional three state data bus lines conn...

Page 20: ...l signals for the other functional blocks of the 82C54 A1 and A0 select one of the three counters or the Con trol Word Register to be read from written into A low on the RD input tells the 82C54 that...

Page 21: ...ontrol Logic to drive the inter nal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read when ever you read the count it is the OL that is...

Page 22: ...the A1 A0 inputs and each Control Word specifies the Counter it applies to SC0 SC1 bits no special instruction sequence is required Any programming sequence that follows the conventions above is accep...

Page 23: ...ultiple Counter Latch Commands may be used to latch more than one Counter Each latched Counter s OL holds its count until read Counter Latch Commands do not affect the programmed Mode of the Counter i...

Page 24: ...s been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the counter is loaded into the counting ele...

Page 25: ...l be loaded on the next CLK pulse and counting will continue from the new count If a two byte count is written the following happens 1 Writing the first byte disables counting Out is set low immediate...

Page 26: ...reloads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables cou...

Page 27: ...ally high The initial count is loaded on one CLK pulse decremented by one on the next CLK pulse and then decremented by two on succeeding CLK pulses When the count expires OUT goes low and the Counter...

Page 28: ...a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this Gate The GATE input is always sampled on the ris...

Page 29: ...h the initial count and continues counting from there FIGURE 15 GATE PIN OPERATIONS SUMMARY FIGURE 16 MINIMUM AND MAXIMUM INITIAL COUNTS SIGNAL STATUS MODES LOW OR GOING LOW RISING HIGH 0 Disables Cou...

Page 30: ...A 5 CP82C55A 40 Ld PDIP 0oC to 70oC E40 6 IP82C55A 5 IP82C55A 40oC to 85oC E40 6 CS82C55A 5 CS82C55A 44 Ld PLCC 0oC to 70oC N44 65 IS82C55A 5 IS82C55A 40oC to 85oC N44 65 CD82C55A 5 CD82C55A 40 Ld CER...

Page 31: ...signal used by the CPU to load control words and data into the 82C55A A0 A1 8 9 I ADDRESS These input signals in conjunction with the RD and WR inputs control the selection of one of the three ports...

Page 32: ...rent of 400 A Group A and Group B Controls The functional configuration of each port is programmed by the systems software In essence the CPU outputs a con trol word to the 82C55A The control word con...

Page 33: ...input mode with no additional ini tialization required This eliminates the need to pullup or pull down resistors in all CMOS designs The control word register will contain 9Bh During the execution of...

Page 34: ...d from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C This function allows the programmer to enable or disable a CP...

Page 35: ...A0 OUTPUT 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 8 PA7 PA0 4 PC7 PC4 4 PC3 PC0 8 PB7 PB0 D7 D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 8 PA7 PA0 4 PC7 PC4 4 PC3 PC0 8 PB7 PB0 D7 D0 82C5...

Page 36: ...3 0 D2 0 D1 1 D0 8 PA7 PA0 4 PC7 PC4 4 PC3 PC0 8 PB7 PB0 D7 D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 8 PA7 PA0 4 PC7 PC4 4 PC3 PC0 8 PB7 PB0 D7 D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 1 D3...

Page 37: ...ndicates that the data has been loaded into the input latch in essence and acknowledg ment IBF is set by STB input being low and is reset by the rising edge of the RD input CONTROL WORD 12 CONTROL WOR...

Page 38: ...data from Port A or Port B is ready to be accepted In essence a response from the peripheral device indicating that it is ready to accept data See Note 1 INTR Interrupt Request A high on this output c...

Page 39: ...n this input enables the three state output buffer of port A to send out the data Oth erwise the output buffer will be in the high impedance state INTE 1 The INTE flip flop associated with OBF Con tro...

Page 40: ...4 D3 D2 D1 D0 CONTROL WORD 1 0 1 0 1 1 0 PC2 PC0 1 INPUT 0 OUTPUT PORT B 1 INPUT 0 OUTPUT GROUP B MODE 0 MODE 0 1 MODE 1 PC7 OBFA PC6 INTE PA7 PA0 ACKA IBFA PC4 WR INTE RD PC3 PC5 PC2 PC0 1 2 8 STBA 3...

Page 41: ...PB0 0 1 1 0 8 WR 1 D7 1 D6 D5 D4 D3 D2 D1 D0 CONTROL WORD PC7 8 STBA PA7 PA0 OBFA IBFA PC5 PC2 PC0 3 RD PC2 PC0 1 INPUT 0 OUTPUT ACKA PC6 INTRA PC3 I O PC4 PB7 PB0 0 0 1 0 8 WR 1 D7 1 D6 D5 D4 D3 D2 D...

Page 42: ...to the correspond ing Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illustrated in Figure 17 Current...

Page 43: ...ware interface between the device and the CPU The functional definition of the 82C55A is programmed by the I O service routine and becomes an extension of the system software By examining the I O devi...

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