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Diamond Systems Corporation GPIO-MM FPGA Pinout Guide V1.01

Page 7

DIO_J3_45

D8

I/O

J3 pin 45

Digital I/O

DIO_J3_46

C8

I/O

J3 pin 46

Digital I/O

DIO_J3_47

D9

I/O

J3 pin 47

Digital I/O

DIO_J3_48

D10

I/O

J3 pin 48

Digital I/O

J4 EXTERNAL SIGNAL GROUP

DIO_J4_1

T14

I/O

J4 pin 1 (U2)

Digital I/O

DIO_J4_2

R11

I/O

J4 pin 2 (U3)

Digital I/O

DIO_J4_3

R13

I/O

J4 pin 3 (U2)

Digital I/O

DIO_J4_4

T11

I/O

J4 pin 4 (U3)

Digital I/O

DIO_J4_5

T13

I/O

J4 pin 5 (U2)

Digital I/O

DIO_J4_6

N11

I/O

J4 pin 6 (U3)

Digital I/O

DIO_J4_7

P13

I/O

J4 pin 7 (U2)

Digital I/O

DIO_J4_8

P11

I/O

J4 pin 8 (U3)

Digital I/O

DIO_J4_9

N12

I/O

J4 pin 9 (U2)

Digital I/O

DIO_J4_10

M11

I/O

J4 pin 10 (U3)

Digital I/O

DIO_J4_11

P12

I/O

J4 pin 11 (U2)

Digital I/O

DIO_J4_12

M10

I/O

J4 pin 12 (U3)

Digital I/O

DIO_J4_13

R12

I/O

J4 pin 13 (U2)

Digital I/O

DIO_J4_14

N10

I/O

J4 pin 14 (U3)

Digital I/O

DIO_J4_15

T12

I/O

J4 pin 15 (U2)

Digital I/O

DIO_J4_16

P10

I/O

J4 pin 16 (U3)

Digital I/O

DIO_J4_17

T9

I/O

J4 pin 17 (U4)

Digital I/O

DIO_J4_18

R7

I/O

J4 pin 18 (U5)

Digital I/O

DIO_J4_19

R9

I/O

J4 pin 19 (U4)

Digital I/O

DIO_J4_20

T7

I/O

J4 pin 20 (U5)

Digital I/O

DIO_J4_21

T10

I/O

J4 pin 21 (U4)

Digital I/O

DIO_J4_22

P7

I/O

J4 pin 22 (U5)

Digital I/O

DIO_J4_23

R10

I/O

J4 pin 23 (U4)

Digital I/O

DIO_J4_24

N7

I/O

J4 pin 24 (U5)

Digital I/O

DIO_J4_25

N9

I/O

J4 pin 25 (U4)

Digital I/O

DIO_J4_26

M7

I/O

J4 pin 26 (U5)

Digital I/O

DIO_J4_27

P9

I/O

J4 pin 27 (U4)

Digital I/O

DIO_J4_28

M6

I/O

J4 pin 28 (U5)

Digital I/O

DIO_J4_29

P8

I/O

J4 pin 29 (U4)

Digital I/O

DIO_J4_30

P6

I/O

J4 pin 30 (U5)

Digital I/O

DIO_J4_31

T8

I/O

J4 pin 31 (U4)

Digital I/O

DIO_J4_32

N6

I/O

J4 pin 32 (U5)

Digital I/O

DIO_J4_33

T6

I/O

J4 pin 33 (U6)

Digital I/O

DIO_J4_34

T2

I/O

J4 pin 34 (U7)

Digital I/O

DIO_J4_35

R6

I/O

J4 pin 35 (U6)

Digital I/O

DIO_J4_36

R1

I/O

J4 pin 36 (U7)

Digital I/O

DIO_J4_37

T5

I/O

J4 pin 37 (U6)

Digital I/O

DIO_J4_38

P1

I/O

J4 pin 38 (U7)

Digital I/O

DIO_J4_39

R5

I/O

J4 pin 39 (U6)

Digital I/O

DIO_J4_40

N2

I/O

J4 pin 40 (U7)

Digital I/O

DIO_J4_41

P5

I/O

J4 pin 41 (U6)

Digital I/O

DIO_J4_42

N1

I/O

J4 pin 42 (U7)

Digital I/O

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Summary of Contents for GPIO-MM

Page 1: ...GPIO MM FPGA based PC 104 FPGA Pinout Guide V1 01 Copyright 2007 Diamond Systems Corporation 1255 Terra Bella Ave Mountain View CA 94043 Tel 650 810 2500 Fax 650 810 2525 www diamondsystems com ...

Page 2: ...104 CONNECTORS J1 AND J2 3 1 2 EXTERNAL I O CONNECTORS J3 J4 J5 AND J6 3 1 3 JUMPER CONFIGURATION BLOCKS J7 J8 J9 AND J10 3 1 4 40MHZ OSCILLATOR Y1 5 1 5 STATUS LED D1 5 1 6 XCF02S CONFIGURATION PROM U9 5 1 7 256 BYTE 24C04 EEPROM U12 5 1 8 74XX164 SHIFT REGISTER U11 5 1 9 74XX245 BUFFERS U2 U7 5 2 PIN DEFINITIONS 6 ...

Page 3: ... lines The FPGA I O lines are connected to J4 through 74XX245 buffers described below J6 is the JTAG port used to program the FPGA and the configuration PROM 1 3 Jumper configuration blocks J7 J8 J9 and J10 J7 and J9 route IRQs as shown below The IRQA and IRQB signals connect to the FPGA and can be routed through jumpers to the IRQx signals on the PC 104 bus The IRQPDA and IRQPDB positions allow t...

Page 4: ... for the I O on J3 and is not related to the FPGA pinout J10 provides user defined configuration jumpers In the drawing above SP_PS1 CFG3 SP_PS0 CFG2 RS4XX CFG1 and RS232 CFG0 Each of the CFG 9 0 signals are connected to an FPGA input pin If the jumper is not present on J10 the signal will be pulled up to 3 3V If the jumper is present the signal is pulled low to 0V These inputs can be used for any...

Page 5: ... The eight outputs lines of the 74XX164 each drive one LED on the lower left side of the board This is used in the standard logic to display the current personality ID but can be used for any purpose in a custom FPGA design It is connected to the FPGA through 2 wires 1 9 74XX245 buffers U2 U7 These buffers sit between J4 and the FPGA and provide higher I O current capability to J4 than the FPGA co...

Page 6: ...18 Digital I O DIO_J3_19 E4 I O J3 pin 19 Digital I O DIO_J3_20 D1 I O J3 pin 20 Digital I O DIO_J3_21 D2 I O J3 pin 21 Digital I O DIO_J3_22 C1 I O J3 pin 22 Digital I O DIO_J3_23 C2 I O J3 pin 23 Digital I O DIO_J3_24 B1 I O J3 pin 24 Digital I O DIO_J3_25 A2 I O J3 pin 25 Digital I O DIO_J3_26 B3 I O J3 pin 26 Digital I O DIO_J3_27 A3 I O J3 pin 27 Digital I O DIO_J3_28 B4 I O J3 pin 28 Digital...

Page 7: ...3 Digital I O DIO_J4_17 T9 I O J4 pin 17 U4 Digital I O DIO_J4_18 R7 I O J4 pin 18 U5 Digital I O DIO_J4_19 R9 I O J4 pin 19 U4 Digital I O DIO_J4_20 T7 I O J4 pin 20 U5 Digital I O DIO_J4_21 T10 I O J4 pin 21 U4 Digital I O DIO_J4_22 P7 I O J4 pin 22 U5 Digital I O DIO_J4_23 R10 I O J4 pin 23 U4 Digital I O DIO_J4_24 N7 I O J4 pin 24 U5 Digital I O DIO_J4_25 N9 I O J4 pin 25 U4 Digital I O DIO_J4...

Page 8: ...104 Bus Clock PC 104 BUS AND CONFIGURATION GROUP IOW C13 In PC 104 B13 I O Write Strobe IOR B13 In PC 104 B14 I O Read Strobe IOCS16 A14 I O PC 104 D2 16 bit I O Access AEN H16 In PC 104 A11 Address Enable SMEMWR D12 In PC 104 B11 Memory Write 1MB SMEMRD C12 In PC 104 B12 Memory Read 1MB MEMWR B12 In PC 104 C10 Memory Write MEMRD A12 In PC 104 C9 Memory Read MEMCS16 A13 I O PC 104 D1 16 bit Memory...

Page 9: ... A4 Data Bus SD4 K14 I O PC 104 A5 Data Bus SD3 K12 I O PC 104 A6 Data Bus SD2 J14 I O PC 104 A7 Data Bus SD1 J15 I O PC 104 A8 Data Bus SD0 J16 I O PC 104 A9 Data Bus IRQB L15 Out J9 IRQB Output IRQA L16 Out J7 IRQA Output CFG9 D11 In J10 Configuration Input CFG8 C11 In J10 Configuration Input CFG7 E11 In J10 Configuration Input CFG6 B11 In J10 Configuration Input CFG5 A11 In J10 Configuration In...

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