DMM-16R-AT User Manual V1.31
www.diamondsystems.com
Page 18
Base + 9
Write
Control Register
Bit No.
7
6
5
4
3
2
1
0
Name
AINTE
TINTE
RSVD
CLKEN CLKSEL
AINTE
Analog interrupt enable:
1
Enable A/D interrupts
0
Disable A/D interrupts
TINTE
Timer interrupt enable:
1
Enable interrupts from timer 0
0
Disable interrupts from timer 0
:
Both AINTE and TINTE should not be set concurrently. Only one interrupt operation at a time is
supported by the board.
RSVD
DMA enable (reserved for future implementation, not currently supported)
CLKEN
Enable hardware A/D clock:
1
Enable hardware A/D trigger (source is selected with CLKSEL bit); software triggers are
disabled
0
Disable hardware trigger; A/D is triggered via software write to Base + 0
CLKSEL
A/D clock select, used only when CLKEN = 1:
1
Internal trigger: Counter/timer (82C54) generates A/D conversions
0
External trigger: PA0, pin 48 on I/O connector J3, generates A/D conversions. This
feature would work only if Port A is input port.
Base + 9
Read
Control readback
Bit No.
7
6
5
4
3
2
1
0
Name
AINTE
EXTPG
PAGE
DMODE
TINTE
RSVD
CLKEN CLKSEL
This register may be used to read the values of various control bits described above. Note that the PAGE bit is
duplicated here and in register 10. If EXTPG = 0, then the PAGE bit reads back the current page setting 0 or 1. If EXTPG
= 1, then the FPGA is forced into page 2 and PAGE reads back as 0. However its register contents are preserved, so
that later when EXTPG returns to 0 the page returns to its previous setting of 0 or 1.
DMODE Digital I/O Mode selection; this determines if the DIO ports function in legacy mode or enhanced mode.
Pin P_DMODE along with the active host bus determine the value of DMODE as follows:
Bus
P_DMODE
DMODE
Meaning
ISA
0
0
Legacy
ISA
1
1
Advanced
PCI
X
1
Advanced
0 Legacy Mode:
Port A is in fixed input mode, and pins PA7-0 are set to input. Port B is in fixed output mode, and
pins PB7-0 are set to output. P_DIRA = 0 and P_DIRB= 1.
1
Enhanced Mode:
The direction of PA7-0 and PB7-0, and pins P_DIRA and P_DIRB, are determined by register
bits DIRA and DIRB