Athena IIII User Manual Rev A.00
www.diamondsystems.com
Page
49
Base + 4
Read/Write
Interrupt / Counter Control
Bit No.
7
6
5
4
3
2
1
0
Name
CKSEL1 FRQSEL1 FRQSEL0 ADCLK
DMAEN
TINTE
DINTE
AINTE
Reset
0
0
0
0
0
0
0
0
CKSEL1
Clock source selection for counter/timer 1:
0 = internal oscillator, frequency selected by CLKFRQ1
1 = external clock input CLK1 (DIO C pins must be set for ctr/timer signals)
FRQSEL1 Input frequency selection for counter/timer 1 when CKSEL1 = 1:
0 = 10MHz, 1 = 100KHz
FRQSEL0 Input frequency selection for counter/timer 0.
0 = 10MHz, 1 = 1MHz
ADCLK
A/D trigger select when AINTE = 1:
0 = internal clock output from counter/timer 0
1 = external clock input EXTTRIG
DMAEN
Enable DMA operation. 1 = enable, 0 = disable.
TINTE
Enable timer interrupts. 1 = enable, 0 = disable.
DINTE
Enable digital I/O interrupts. 1 = enable, 0 = disable.
AINTE
Enable analog input interrupts. 1 = enable, 0 = disable.
NOTE:
When AINTE = 1, the A/D cannot be triggered by writing to Base + 0.
Analog output interrupts are not supported on this board.
Multiple interrupt operations may be performed simultaneously. All interrupts will be on the same interrupt
level. The user’s interrupt routine must monitor the status bits to know which circuit has requested service.
After processing the data but before exiting, the interrupt routine must then clear the appropriate interrupt
request bit using the register at Base + 0.