User Guide DA7212_Rev1v2 CONFIDENTIAL
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User Guide
DA7212 User Guide – Rev1.2
DAI and PLL Page
The DAI and PLL page allows control of the digital audio interface and phase-
locked loop. The DAI CTRL panel sets the format on the DAI and the DAI CLK
MODE panel sets the master/slave mode as well as the clock polarity and
number of BCLKS per WCLK. The DIG ROUTING DAI panel selects the data
source for the DAI and DIG ROUTING DAC selects the data source for the
DAC.
The PLL Control panel contains all the settings for the PLL and on-chip
clocking. The SR panel sets the sample rate being used. The PLL CTRL
panel sets the input clock rate, whether the PLL is enabled and whether
sample rate matching (SRM) is required to track the DAI in slave mode. If the
PLL is required, the three FBDIV panels control the value of the feedback
divider. The required values can be calculated using the DA7212 PLL
Calculator spreadsheet, or they can be determined automatically by entering
the supplied MCLK frequency and pressing the Calculate PLL button. The
current status of the PLL is shown in the PLL STATUS panel. The PC COUNT
panel controls the behavior of the internal program counter.
