dg_toeudp10gip_fpgasetup_intel.doc
26-Aug-20
Page 12
2 Test environment setup when using two FPGAs
Before running the test, please prepare following test environment.
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Two FPGA development boards which are the same board or different board,
Arria10 SoC/Arria10 GX/Cyclone10 GX/Stratix10 GX (H-Tile) development board
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10Gb Ethernet cable:
a) 10 Gb SFP+ Active Optical Cable (AOC)
b) 2x10 Gb SFP+ transceiver (10G BASE-R) with optical cable (LC to LC, Multimode)
c) For Stratix10 GX board, QSFP+ to four SFP+ cable
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Two micro USB cables, one cable for connecting one FPGA board to PC
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QuartusII Programmer for programming FPGA and NiosII command shell, installed on PC
Figure 2-1 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->FPGA)