DG TOE10G-IP Setup Manual Download

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dg_toeudp10gip_fpgasetup_intel.doc

26-Aug-20

Page 12

2 Test environment setup when using two FPGAs

Before running the test, please prepare following test environment.

•

Two FPGA development boards which are the same board or different board,

Arria10 SoC/Arria10 GX/Cyclone10 GX/Stratix10 GX (H-Tile) development board

•

10Gb Ethernet cable:

a)  10 Gb SFP+ Active Optical Cable (AOC)
b)  2x10 Gb SFP+ transceiver (10G BASE-R) with optical cable (LC to LC, Multimode)
c)  For Stratix10 GX board, QSFP+ to four SFP+ cable

•

Two micro USB cables, one cable for connecting one FPGA board to PC

•

QuartusII Programmer for programming FPGA and NiosII command shell, installed on PC

Figure 2-1 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->FPGA)

Summary of Contents for TOE10G-IP

Page 1: ...Figure 1 1 Figure 1 1 Two test environments for running the demo First uses one FPGA board and Test PC with 10Gb Ethernet card for transferring the data TestPC runs test application i e tcpdatatest half duplex test for TOE10G IP tcp_client_txrx_40G full duplex test for TOE10G IP or udpdatatest test application for UDP10G IP Also NiosII terminal is run on Test PC to be user interface console Second...

Page 2: ...ratix10 GX board only QSFP to four SFP cable micro USB cable for JTAG connection Test application provided by Design Gateway for running on Test PC TOE10G IP tcpdatatest exe and tcp_client_txrx_40G exe UDP10G IP udpdatatest exe QuartusII Programmer and NiosII command shell installed on PC Note Example hardware for running the demo is listed as follows 1 10G Network Adapter Intel X520 DA2 http www ...

Page 3: ...n Arria10 SoC Note Four LEDs are applied to show IP timeout status when the configuration file of the demo uses 1 hour timeout TOE10G IP UDP10G IP After running for 1 hour the IP stops the operation All LEDs are blinked to notify that the IP now is timeout User needs to reconfigure FPGA to restart the test ...

Page 4: ...dg_toeudp10gip_fpgasetup_intel doc 26 Aug 20 Page 4 Figure 1 2 TOE10G IP UDP10G IP with CPU demo FPGA PC on Arria10 GX ...

Page 5: ...dg_toeudp10gip_fpgasetup_intel doc 26 Aug 20 Page 5 Figure 1 3 TOE10G IP UDP10G IP with CPU demo FPGA PC on Cyclone10 GX ...

Page 6: ...dg_toeudp10gip_fpgasetup_intel doc 26 Aug 20 Page 6 Figure 1 4 TOE10G IP UDP10G IP with CPU demo FPGA PC on Stratix10 GX ...

Page 7: ...TAG programming and JTAG UART Figure 1 5 Power connection and microUSB connection 3 Connect 10Gb Ethernet cable between FPGA board and PC a For every board except Stratix10 GX board insert 10 Gb SFP DAC Length 1m AOC or SFP transceiver with LC LC cable between FPGA board and PC b For Stratix10 GX board insert QSFP to 4 SFP cable between FPGA board and PC Use SFP no 1 to connect to QSFP1 connector ...

Page 8: ...ammable clock to 322 265625 MHz by using Clock Control application as following step a Open Clock Controller application b Select Si5338 tab U50 and set CLK3 frequency 322 265625 MHz c Click Set button and wait until the application is active again d Close Clock controller application Figure 1 7 Reference clock programming ...

Page 9: ...ware Setup to select USB BlasterII USB 1 b Click Auto Detect and select FPGA number c Select Arria 10 Cyclone 10 Stratix 10 device icon d Click Change File button select SOF file in pop up window and click open button e Check program f Click Start button to program FPGA g Wait until Progress status is equal to 100 Figure 1 8 FPGA Programmer ...

Page 10: ...DP10G IP in client mode asking PC MAC address by sending ARP request c Default parameter in client mode is displayed on the console Figure 1 10 Message after system boot up If Ethernet connection has the problem and the status is linked down the error message is displayed on the console instead of welcome message as shown in Figure 1 11 Figure 1 11 Error message when cable is linked down ...

Page 11: ...Figure 1 12 If user enters other keys the menu for changing parameter is displayed similar to Reset TCPIP parameters menu The example when running the main menu is described in dg_toe10gip_cpu_instruction or dg_udp10gip_cpu_instruction document Figure 1 12 Initialization complete Note Transfer performance in the demo depends on Test PC specification in Test platform ...

Page 12: ...C Arria10 GX Cyclone10 GX Stratix10 GX H Tile development board 10Gb Ethernet cable a 10 Gb SFP Active Optical Cable AOC b 2x10 Gb SFP transceiver 10G BASE R with optical cable LC to LC Multimode c For Stratix10 GX board QSFP to four SFP cable Two micro USB cables one cable for connecting one FPGA board to PC QuartusII Programmer for programming FPGA and NiosII command shell installed on PC Figure...

Page 13: ...rogramming clock to 322 265625 MHz could be used when only one FPGA is connected to PC User connects one micro USB cable to set clock on one Arria 10 SoC board at a time If two Arria 10 SoC boards are used in the test user must switch micro USB cable to program clock on the 2nd board after finishing the 1st board setting After that two micro USB cables for connecting two FPGA boards to PC are allo...

Page 14: ...USB connections with two FPGA boards Follow step 6 of topic 1 Test environment setup when using FPGA and PC for FPGA configuration Figure 2 3 Two USB Blaster cables when connecting two FPGA boards to PC 3 Open QuartusII Programmer to program FPGA board 1 by using USB 1 connection and then switch to program FPGA board 2 by using USB 2 connection Figure 2 4 Select USB BlasterII ...

Page 15: ...cable 2 command for FPGA 2 Figure 2 5 Run NiosII terminal on two consoles 5 Set the input to the console a Set 1 on Serial console of FPGA board 1 for running server mode b Set 0 on Serial console of FPGA board 2 for running client mode c Default parameters for server or client are displayed on the console as shown in Figure 2 6 Figure 2 6 Input mode ...

Page 16: ...mode must be set before client mode When running TOE10G IP a Set parameters on server Serial console b Set parameters on client Serial console to start IP initialization by transferring ARP packet c After finishing initialization process IP initialization complete and main menu are displayed on server console and client console Figure 2 7 Main menu ...

Page 17: ...arameters input x to skip parameter setting b For client mode user must change target port number Target FPGA to use same value as target port number FPGA Target c After finishing initialization process IP initialization complete and main menu are displayed on server console and client console Figure 2 8 Main menu of UDP10G IP ...

Page 18: ...7 Mar 18 Add Part A FPGA PC test 1 2 4 Apr 18 Correct optical cable in Figures and the descriptions 1 3 5 Feb 19 Add Arria 10 GX board and change software to tcp_client_txrx_40G 1 4 31 May 19 Add timeout LED descriptions 1 5 20 Aug 19 Add Cyclone10 GX board 2 0 18 Jun 20 Remove test result on the console 3 0 26 Aug 20 TOE10G IP and UDP10G IP ...

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