PCI/ISA System Board
17
Cache Configuration
The G586OPC system board can support either asyn-
chronous cache SRAM or synchronous (pipelined
burst) cache SRAM. Three cache sizes are supported:
256KB, 512KB and 1MB. 256KB is the default size.
Installing Asynchronous Cache SRAM
The SRAM sockets allow you to install either 32Kx8,
64Kx8 or 128Kx8 SRAM. Regardless of the amount of
cache memory installed, one 32Kx8 (U23) is needed for
tag RAM to store the cacheable addresses. The locations
of the SRAM sockets on the system board are shown on
the next page.
SRAM Socket
Summary of Contents for G586OPC
Page 1: ...G586OPC Rev 0 SystemBoard User sManual D28450828...
Page 15: ...G586OPC 10 VRMHeader Pin 1 of the SIMM socket Locations of the SIM Sockets on the System Board...
Page 23: ...G586OPC 18 Pin1oftheSRAM socket...
Page 37: ...G586OPC JumperSettingsforCPU 32 LocationsofJumpersJP7 JP8 JP16andJP17 ontheG586OPCSystemBoard...
Page 62: ...PCI ISASystemBoard 57 ExpansionSlotsontheG586OPC SystemBoard Master Slave...
Page 69: ...G586OPC v AppendixC ConnectorPinAssignments 64 HJ1 J2...
Page 79: ...G586OPC...
Page 80: ...G586OPC Rev 0 SystemBoard User sManual...
Page 81: ...G586OPC Rev 0 SystemBoard User sManual 28450828...
