66
3
Award BIOS Setup Utility
3.1.3.9 System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM
addressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
3.1.3.10 Video BIOS Cacheable
As with caching the system BIOS, enabling the Video BIOS cache
will allow access to video BIOS addresssed at C0000H to
C7FFFH to be cached, if the cache controller is also enabled. The
larger the range of the Cache RAM, the faster the video perform-
ance.
3.1.3.11 Memory Hole At 15M-16M
In order to improve system performance, certain space in memory
can be reserved for ISA cards. This memory must be mapped into
the memory space below 16MB. When enabled, the CPU assumes
the 15-16MB memory range is allocated to the hidden ISA address
range instead of the actual system DRAM. When disabled, the CPU
assumes the 15-16MB address range actually contains DRAM
memor y. If more than 16MB of system memor y is installed, this
field must be disabled to provide contiguous system memory.
3.1.3.12 Delayed Transaction
When enabled, this function frees up the PCI bus for other PCI
masters during the PCI-to-ISA transactions. This allows PCI and
ISA buses to be used more efficiently and prevents degradation
of performance on the PCI bus when ISA accesses are made.
3.1.3.13 Delay Prior To Thermal
This field is used to select the time that would force the CPU to
a 50% duty cycle when it exceeds its maximum operating tem-
perature therefore protecting the CPU and the system board
from overheating to ensure a safe computing environment..
3.1.3.14 AGP Aperture Size (MB)
This field is relevant to the memory-mapped graphics data of the
AGP card installed in your system. Leave this in its default setting.
