29
Chapter 2
HARDWARE INSTALLATION
User's Manual |
CMS330
SMBus Connector
X
Internal I/O Connectors
LPC Connector
X
Internal I/O Connectors
DDR4_1
DDR4_2
DDR4_3
DDR4_4
LGA 1200
PCIE1 (PCIe x16)
PCI1
PCI2
PCIE2 (PCIe x4)
USB 7/8
(USB 2.0)
Mic In
Line Out
Line In
Note
LAN1
USB 1/2
(USB 3.2 Gen 2)
LAN2
USB 3/4
(USB 3.2 Gen 1)
USB 7/8/9/10
(USB 3.2 Gen 1)
Buzzer
Battery
Intel
H420E/Q470E
ATX
power
Standby
Power
LED
1
13
12
24
1
2
10
1
2
10
USB 9/10 (USB 2.0)
USB 11/12
(USB 2.0)
Note
S/PDIF
1
2
19
M.2 E Key
2230
SATA0/1/2/3
(top to bottom)
SYS FAN2
1
M.2 M Key
2242
2260
2280
SYS FAN1 CPU FAN1
1
1
COM2/3/4/5
(top to bottom)
1
2
13
LPC
14
9
1
2
Front
Panel
1
2
11
SPI Flash
BIOS
1
LAN LED
Digital I/O (DIO)
Front
Audio
1
2
10
7
1
8
2
9
+12V Power
1
5
1
J10
HDMI
DP
VGA
9
1
9
1
9
1
SYS FAN3
1
1
2
5
J12
3
1
3
1
3
1
J34
1
9
J35
1
9
2
J36
1
9
J37
1
9
1
3
1
4
JP26
1
3
JP5
11
1
10
20
USB 3.2 Gen1
(USB 5/6)
JP24
HDDPWR
6
5
2
1
JP4/2/3/1
(top to bottom)
6
5
2
1
6
5
2
1
6
5
2
1
DIO Power
1
4
COM 6
1
2
9
JP13/11/25
(left to right)
6
5
2
1
1
SOJ2
1
2
5
GND
SMB_DATA
SMB_CLK
3V3DU
SMB_ALERT
SMBus
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
DDR4_1
DDR4_2
DDR4_3
DDR4_4
LGA 1200
PCIE1 (PCIe x16)
PCI1
PCI2
PCIE2 (PCIe x4)
USB 7/8
(USB 2.0)
Mic In
Line Out
Line In
Note
LAN1
USB 1/2
(USB 3.2 Gen 2)
LAN2
USB 3/4
(USB 3.2 Gen 1)
USB 7/8/9/10
(USB 3.2 Gen 1)
Buzzer
Battery
Intel
H420E/Q470E
ATX
power
Standby
Power
LED
1
13
12
24
1
2
10
1
2
10
USB 9/10 (USB 2.0)
USB 11/12
(USB 2.0)
Note
S/PDIF
1
2
19
M.2 E Key
2230
SATA0/1/2/3
(top to bottom)
SYS FAN2
1
M.2 M Key
2242
2260
2280
SYS FAN1 CPU FAN1
1
1
COM2/3/4/5
(top to bottom)
1
2
13
LPC
14
9
1
2
Front
Panel
1
2
11
SPI Flash
BIOS
1
LAN LED
Digital I/O (DIO)
Front
Audio
1
2
10
7
1
8
2
9
+12V Power
1
5
1
J10
HDMI
DP
VGA
9
1
9
1
9
1
SYS FAN3
1
1
2
5
J12
3
1
3
1
3
1
J34
1
9
J35
1
9
2
J36
1
9
J37
1
9
1
3
1
4
JP26
1
3
JP5
11
1
10
20
USB 3.2 Gen1
(USB 5/6)
JP24
HDDPWR
6
5
2
1
JP4/2/3/1
(top to bottom)
6
5
2
1
6
5
2
1
6
5
2
1
DIO Power
1
4
COM 6
1
2
9
JP13/11/25
(left to right)
6
5
2
1
1
SOJ2
13
14
1
2
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s transi-
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the
pin functions of the LPC connector.
Pin Assignment
Pin Assignment
1
CLK
2
LAD1
3
RST#
4
LAD0
5
FRAME#
6
VCC3
7
LAD3
8
GND
9
LAD2
10
---
11
SERIRQ
12
GND
13
5V5B
14
5V
