DFI CMS310-Q470E, User Manual

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28
Chapter 2
HARDWARE INSTALLATION
User's Manual | CMS310
SMBus Connector
X
Internal I/O Connectors
LPC Connector
X
Internal I/O Connectors
DDR4_1 DDR4_2
DDR4_3 DDR4_4
LGA 1200
PCIE1 (PCIe x16)
PCIE2 (PCIe x16)
PCIE3 (PCIe x4)
PCIE4 (PCIe x4)
USB 3/4
DP+
Mic In
Line Out
Line In
Note
LAN4
USB 7/8
(USB 3.1 Gen 2)
LAN3
USB 1/2
(USB 3.1 Gen 1)
Buzzer
Battery
Intel
W480E/Q470E
ATX
power
Standby
Power
LED
1 13
12 24
1
2 10
1
2 10
USB 9/10 (USB 2.0)
S/PDIF
JP5
USB 11/12
(USB 2.0)
Note
1
10
11
M.2 E Key
2230
SATA2/3
(left/right)
SATA0/1
(left/right)
SYS FAN3 SYS FAN2
1 1
M.2 M Key
2242 2260 2280
SYS FAN1 CPU FAN1
1
1
1 2
13
LPC
COM1/2/3/4
(top to bottom)
14
9 1
2
Front
Panel
Front LAN
LED 1/2
1 2
11
1
2
7
8
SPI Flash
BIOS
1
Digital I/O (DIO)
Front
Audio
1
2
10 9
+12V Power
1
5
1
2
5
6
1
2
5
6
JP10/8/6/7
(left to right)
1
2
5
6
1
2
5
6
1
DP/COM1
HDMI
VGA
11
1 10
20
USB 3.2 Gen 2
(USB 5/6)
LAN 1/2
9 1
9 1
9 1
PS2
1 2
9
1
2
5
6
1
2
5
6
1
2
5
6
1
2
5
6
JP1 JP2
JP3 JP4
1
2
5
J12
1
2
7
8
Front LAN
LED 3/4
3
1
3
1
3
1
3
1
3
JP14/13/12/11
(right to left)
1
3
JP26
1
2
5
6
JP27
20
1
DIO Power
2
2
2
1
3
JP15
2 1
CASE
OPEN
1
JP24
1 2
5
GND
SMB_DATA SMB_CLK
3V3DU
SMB_ALERT
„
SMBus
The SMBus (System Management Bus) connector is used to connect SMBus devices. It is a
multiple device bus that allows multiple chips to connect to the same bus and enable each one
to act as a master by initiating data transfer.
DDR4_1 DDR4_2
DDR4_3 DDR4_4
LGA 1200
PCIE1 (PCIe x16)
PCIE2 (PCIe x16)
PCIE3 (PCIe x4)
PCIE4 (PCIe x4)
USB 3/4
DP+
Mic In
Line Out
Line In
Note
LAN4
USB 7/8
(USB 3.1 Gen 2)
LAN3
USB 1/2
(USB 3.1 Gen 1)
Buzzer
Battery
Intel
W480E/Q470E
ATX
power
Standby
Power
LED
1 13
12 24
1
2 10
1
2 10
USB 9/10 (USB 2.0)
S/PDIF
JP5
USB 11/12
(USB 2.0)
Note
1 10
11
M.2 E Key
2230
SATA2/3
(left/right)
SATA0/1
(left/right)
SYS FAN3 SYS FAN2
1 1
M.2 M Key
2242 2260 2280
SYS FAN1 CPU FAN1
1
1
1 2
13
LPC
COM1/2/3/4
(top to bottom)
14
9 1
2
Front
Panel
Front LAN
LED 1/2
1 2
11
1
2
7
8
SPI Flash
BIOS
1
Digital I/O (DIO)
Front
Audio
1
2
10 9
+12V Power
1
5
1
2
5
6
1
2
5
6
JP10/8/6/7
(left to right)
1
2
5
6
1
2
5
6
1
DP/COM1
HDMI
VGA
11
1 10
20
USB 3.2 Gen 2
(USB 5/6)
LAN 1/2
9 1
9 1
9 1
PS2
1 2
9
1
2
5
6
1
2
5
6
1
2
5
6
1
2
5
6
JP1 JP2
JP3 JP4
1
2
5
J12
1
2
7
8
Front LAN
LED 3/4
3
1
3
1
3
1
3
1
3
JP14/13/12/11
(right to left)
1
3
JP26
1
2
5
6
JP27
20
1
DIO Power
2
2
2
1
3
JP15
2 1
CASE
OPEN
1
JP24
13 14
1 2
„
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s transi-
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the
pin functions of the LPC connector.
Pin Assignment Pin Assignment
1 CLK 2 L_AD1
3 RST# 4 L_AD0
5 FRAME# 6 VCC3
7 LAD3 8 GND
9 LAD2 10 ---
11 SERIRQ 12 GND
13 5V5B 14 5V