DFI CM901-B, User Manual, Page: 20 / 72

www.dfi.com Chapter 3 Hardware Installation
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Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
AC/HAD_RST# A30 O CMOS 3.3V Suspend/3.3V Reset output to CODEC, active low.
AC/HDA_SYNC A29 O CMOS 3.3V/3.3V Sample-synchronization signal to the CODEC(s).
AC/HDA_BITCLK A32 I/O CMOS 3.3V/3.3V Serial data clock generated by the external CODEC(s).
AC/HDA_SDOUT A33 O CMOS 3.3V/3.3V Serial TDM data output to the CODEC.
AC/HDA_SDIN2 B28 I/O CMOS 3.3V Suspend/3.3V
AC/HDA_SDIN1 B29 I/O CMOS 3.3V Suspend/3.3V
AC/HDA_SDIN0 B30 I/O CMOS 3.3V Suspend/3.3V
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
GB A13 I/O Analog 3.3V max Suspend
GBE0_MDI0- A12 I/O Analog 3.3V max Suspend
GB A10 I/O Analog 3.3V max Suspend
GBE0_MDI1- A9 I/O Analog 3.3V max Suspend
GB A7 I/O Analog 3.3V max Suspend
GBE0_MDI2- A6 I/O Analog 3.3V max Suspend
GB A3 I/O Analog 3.3V max Suspend
GBE0_MDI3- A2 I/O Analog 3.3V max Suspend
GBE0_ACT# B2 OD CMOS 3.3V Suspend/3.3V Gigabit Ethernet Controller 0 activity indicator, active low.
GBE0_LINK# A8 OD CMOS 3.3V Suspend/3.3V Gigabit Ethernet Controller 0 link indicator, active low.
GBE0_LINK100# A4 OD CMOS 3.3V Suspend/3.3V Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.
GBE0_LINK1000# A5 OD CMOS 3.3V Suspend/3.3V Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.
GBE0_CTREF A14 REF GND min 3.3V max 1.9V Reference voltage for Carrier Board Ethernet channel 0 magnetics center
tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V.
The reference voltage output shall be current limited on the Module. In
the case in which the reference
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
S A16 O SATA AC coupled on Module
SATA0_TX- A17 O SATA AC coupled on Module
S A19 I SATA AC coupled on Module
SATA0_RX- A20 I SATA AC coupled on Module
S B16 O SATA AC coupled on Module
SATA1_TX- B17 O SATA AC coupled on Module
S B19 I SATA AC coupled on Module
SATA1_RX- B20 I SATA AC coupled on Module
S A22 O SATA AC coupled on Module
SATA2_TX- A23 O SATA AC coupled on Module
S A25 I SATA AC coupled on Module
SATA2_RX- A26 I SATA AC coupled on Module
S B22 O SATA AC coupled on Module
SATA3_TX- B23 O SATA AC coupled on Module
S B25 I SATA AC coupled on Module
SATA3_RX- B26 I SATA AC coupled on Module
ATA_ACT# A28 I/O CMOS 3.3V / 3.3V ATA (parallel and serial) or SAS activity indicator, active low.
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
P A68
PCIE_TX0- A69
P B68
PCIE_RX0- B69
P A64
PCIE_TX1- A65
P B64
PCIE_RX1- B65
P A61
PCIE_TX2- A62
P B61
PCIE_RX2- B62
P A58
PCIE_TX3- A59
P B58
PCIE_RX3- B59
P A55
PCIE_TX4- A56
P B55
PCIE_RX4- B56
P A52
PCIE_TX5- A53
P B52
PCIE_RX5- B53
P D19
PCIE_TX6- D20
P C19
PCIE_RX6- C20
P D22
PCIE_TX7- D23
P C22
PCIE_RX7- C23
PCIE0 A88
PCIE0_CK_REF- A89
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
D52
PEG_TX0- D53
C52
PEG_RX0- C53
D55
PEG_TX1- D56
C55
PEG_RX1- C56
D58
PEG_TX2- D59
C58
PEG_RX2- C59
D61
PEG_TX3- D62
C61
PEG_RX3- C62
D65
PEG_TX4- D66
C65
PEG_RX4- C66
D68
PEG_TX5- D69
C68
PEG_RX5- C69
D71
PEG_TX6- D72
C71
PEG_RX6- C72
D74
PEG_TX7- D75
C74
PEG_RX7- C75
D78
PEG_TX8- D79
C78
PEG_RX8- C79
D81
PEG_TX9- D82
C81
PEG_RX9- C82
P D85
PEG_TX10- D86
P C85
PEG_RX10- C86
P D88
PEG_TX11- D89
P C88
PEG_RX11- C89
P D91
PEG_TX12- D92
P C91
PEG_RX12- C92
P D94
PEG_TX13- D95
P C94
PEG_RX13- C95
P D98
PEG_TX14- D99
P C98
PEG_RX14- C99
P D101
PEG_TX15- D102
P C101
PEG_RX15- C102
PEG_LANE_RV# D54 I CMOS 3.3V / 3.3V PCI Express Graphics lane reversal input strap. Pull low on the Carrier
board to reverse lane order.
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
EXCD0_CPPE# A49
EXCD1_CPPE# B48
EXCD0_PERST# A48
EXCD1_PERST# B47
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
USB0+ A46
USB0- A45
USB1+ B46
USB1- B45
USB2+ A43
USB2- A42
USB3+ B43
USB3- B42
USB4+ A40
USB4- A39
USB5+ B40
USB5- B39
USB6+ A37
USB6- A36
USB7+ B37
USB7- B36
USB_0_1_OC# B44 I CMOS 3.3V Suspend/3.3V PU 10k to 3.3VSB USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB_2_3_OC# A44 I CMOS 3.3V Suspend/3.3V PU 10k to 3.3VSB USB over-current sense, USB channels 2 and 3. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB_4_5_OC# B38 I CMOS 3.3V Suspend/3.3V PU 10k to 3.3VSB USB over-current sense, USB channels 4 and 5. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB_6_7_OC# A38 I CMOS 3.3V Suspend/3.3V PU 10k to 3.3VSB USB over-current sense, USB channels 6 and 7. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
US D4
USB_SSTX0- D3
US C4
USB_SSRX0- C3
US D7
USB_SSTX1- D6
US C7
USB_SSRX1- C6
US D10
USB_SSTX2- D9
US C10
USB_SSRX2- C9
US D13
USB_SSTX3- D12
US C13
USB_SSRX3- C12
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
A71
LVDS_A0- A72
A73
LVDS_A1- A74
A75
LVDS_A2- A76
A78
LVDS_A3- A79
LV A81
LVDS_A_CK- A82
B71
LVDS_B0- B72
B73
LVDS_B1- B74
B75
LVDS_B2- B76
B77
LVDS_B3- B78
LV B81
LVDS_B_CK- B82
LVDS_VDD_EN A77 O CMOS 3.3V / 3.3V LVDS panel power enable
LVDS_BKLT_EN B79 O CMOS 3.3V / 3.3V LVDS panel backlight enable
LVDS_BKLT_CTRL B83 O CMOS 3.3V / 3.3V LVDS panel backlight brightness control
LVDS_I2C_CK A83 I/O OD 3.3V / 3.3V N.C. I2C clock output for LVDS display use
LVDS_I2C_DAT A84 I/O OD 3.3V / 3.3V N.C. I2C data line for LVDS display use
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
LPC_AD0 B4
LPC_AD1 B5
LPC_AD2 B6
LPC_AD3 B7
LPC_FRAME# B3 O CMOS 3.3V / 3.3V LPC frame indicates the start of an LPC cycle
LPC_DRQ0# B8
LPC_DRQ1# B9
LPC_SERIRQ A50 I/O CMOS 3.3V / 3.3V LPC serial interrupt
LPC_CLK B10 O CMOS 3.3V / 3.3V PU 10K LPC clock output - 33MHz nominal
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
SPI_CS# B97 O CMOS 3.3V Suspend/3.3V Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1
SPI_MISO A92 I CMOS 3.3V Suspend/3.3V Data in to Module from Carrier SPI
SPI_MOSI A95 O CMOS 3.3V Suspend/3.3V Data out from Module to Carrier SPI
SPI_CLK A94 O CMOS 3.3V Suspend/3.3V Clock from Module to Carrier SPI
SPI_POWER A91 O 3.3V Suspend/3.3V Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier
BIOS_DIS0# A34
BIOS_DIS1# B88
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
VGA_RED B89 O Analog Analog PD 150Rx2 Red for monitor. Analog output
VGA_GRN B91 O Analog Analog PD 150Rx2 Green for monitor. Analog output
VGA_BLU B92 O Analog Analog PD 150Rx2 Blue for monitor. Analog output
VGA_HSYNC B93 O CMOS 3.3V / 3.3V Horizontal sync output to VGA monitor
VGA_VSYNC B94 O CMOS 3.3V / 3.3V Vertical sync output to VGA monitor
VGA_I2C_CK B95 I/O OD 3.3V / 3.3V PD 2.2K to 3.3V DDC clock line (I2C port dedicated to identify VGA monitor capabilities)
VGA_I2C_DAT B96 I/O OD 3.3V / 3.3V PD 2.2K to 3.3V DDC data line.
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
SER0_TX A98 O CMOS 5V / 12V General purpose serial port 0 transmitter
SER0_RX A99 I CMOS 5V / 12V General purpose serial port 0 receiver
SER1_TX A101 O CMOS 5V / 12V General purpose serial port 1 transmitter
SER1_RX A102 I CMOS 5V / 12V General purpose serial port 1 receiver
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
I2C_CK B33 I/O OD 3.3V Suspend/3.3V PU 2.2K to General purpose I2C port clock output
I2C_DAT B34 I/O OD 3.3V Suspend/3.3V PU 2.2K to General purpose I2C port data I/O line
SPKR B32 O CMOS 3.3V / 3.3V Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.
WDT B27 O CMOS 3.3V / 3.3V Output indicating that a watchdog time-out event has occurred.
FAN_PWNOUT B101 O OD CMOS 3.3V / 12V Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's
RPM.
FAN_TACHIN B102 I OD CMOS 3.3V / 12V PU 10K to 3.3V Fan tachometer input for a fan with a two pulse output.
TPM_PP A96 I CMOS 3.3V / 3.3V Trusted Platform Module (TPM) Physical Presence pin. Active high.
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
PWRBTN# B12 I CMOS 3.3V Suspend/3.3V PU 10K to 3.3VSB A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.
SYS_RESET# B49 I CMOS 3.3V Suspend/3.3V PU 10K to 3.3VSB Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.
CB_RESET# B50 O CMOS 3.3V Suspend/3.3V Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.
PWR_OK B24 I CMOS 3.3V / 3.3V Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.
SUS_STAT# B18 O CMOS 3.3V Suspend/3.3V Indicates imminent suspend operation; used to notify LPC devices.
SUS_S3# A15 O CMOS 3.3V Suspend/3.3V Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.
SUS_S4# A18 O CMOS 3.3V Suspend/3.3V Indicates system is in Suspend to Disk state. Active low output.
SUS_S5# A24 O CMOS 3.3V Suspend/3.3V Indicates system is in Soft Off state.
WAKE0# B66 I CMOS 3.3V Suspend/3.3V PU 10K to 3.3VSB PCI Express wake up signal.
WAKE1# B67 I CMOS 3.3V Suspend/3.3V PU 10K to 3.3VSB General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.
BATLOW# A27 I CMOS 3.3V Suspend/ 3.3V PU 10K to 3.3VSB Indicates that external battery is low.
LID# A103 I OD CMOS 3.3V Suspend/12V PU 10K to 3.3VSB LID switch. Low active signal used by the ACPI operating system for a LID switch.
SLEEP# B103 I OD CMOS 3.3V Suspend/12V PU 10K to 3.3VSB Sleep button. Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.
THRM# B35 I CMOS 3.3V / 3.3V PU 8.2K to 3.3V Input from off-Module temp sensor indicating an over-temp situation.
THRMTRIP# A35 O CMOS 3.3V / 3.3V PU 10K to 3.3V Active low output indicating that the CPU has entered thermal shutdown.
SMB_CK B13 I/O OD 3.3V Suspend/3.3V PU 2.2K to System Management Bus bidirectional clock line.
SMB_DAT B14 I/O OD 3.3V Suspend/3.3V PU 2.2K to System Management Bus bidirectional data line.
SMB_ALERT# B15 I CMOS 3.3V Suspend/3.3V System Management Bus Alert – active low input can be used to
generate an SMI# (System Management Interrupt) or to wake the system.
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
GPO0 A93
GPO1 B54
GPO2 B57
GPO3 B63
GPI0 A54
GPI1 A63
GPI2 A67
GPI3 A85
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
VCC_12V A104~A109
B104~B109
C104~C109
D104~D109 Power Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be
used.
VCC_5V_SBY B84~B87 Power Standby power input: +5.0V nominal. If VCC5_SBY is used, all
available VCC_5V_SBY pins on the connector(s) shall be used. Only
used for standby and suspend functions. May be left unconnected if
these functions are not used in the system design.
VCC_RTC A47 Power Real-time clock circuit-power input. Nom3.0V.
GND A1, A11, A21, A31,
A41, A51, A57,
A60, A66, A70,
A80, A90, A100,
A110, B1, B11, B21
,B31, B41, B51,
B60, B70, B80,
B90, B100, B110,
C1, C2, C5, C8,
C11, C14, C21,
C31, C41, C51,
C60, C70, C73,
C76, C80, C84,
C87, C90, C93,
C96, C100, C103,
C110, D1, D2, D5,
D8, D11, D14, D21,
D31, D51, D60, Power Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier
Board GND plane.
AC97/HDA Signals Descriptions
Serial TDM data inputs from up to 3 CODECs.
Gigabit Ethernet Signals Descriptions
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec
modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
Serial ATA or SAS Channel 1 receive differential pair.
Serial ATA or SAS Channel 2 transmit differential pair.
Serial ATA or SAS Channel 2 receive differential pair.
SATA Signals Descriptions
Serial ATA or SAS Channel 0 transmit differential pair.
Serial ATA or SAS Channel 0 receive differential pair.
Serial ATA or SAS Channel 1 transmit differential pair.
Serial ATA or SAS Channel 3 transmit differential pair.
Serial ATA or SAS Channel 3 receive differential pair.
PCI Express Lanes Signals Descriptions
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 0
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 1
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 2
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 0
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 1
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 3
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 4
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 2
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 3
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 5
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 6
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 4
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 5
I PCIE AC coupled off Module N.C. PCI Express Differential Receive Pairs 7
O PCIE PCIE Reference clock output for all PCI Express and PCI Express Graphics lanes.
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 6
O PCIE AC coupled on Module N.C. PCI Express Differential Transmit Pairs 7
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 1
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 1
PEG Signals Descriptions
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 0
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 0
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 3
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 3
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 2
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 2
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 5
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 5
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 4
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 4
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 7
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 7
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 6
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 6
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 9
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 9
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 8
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 8
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 11
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 11
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 10
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 10
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 13
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 13
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 12
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 12
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 15
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 15
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 14
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 14
ExpressCard Signals Descriptions
I CMOS 3.3V /3.3V PU 10k to 3.3V PCI ExpressCard: PCI Express capable card request, active low, one per card
O CMOS 3.3V /3.3V PCI ExpressCard: reset, active low, one per card
I/O USB 3.3V Suspend/3.3V USB differential pairs 2
I/O USB 3.3V Suspend/3.3V USB differential pairs 3
USB Signals Descriptions
I/O USB 3.3V Suspend/3.3V USB differential pairs 0
I/O USB 3.3V Suspend/3.3V USB differential pairs 1
I/O USB 3.3V Suspend/3.3V USB differential pairs 6
I/O USB 3.3V Suspend/3.3V USB differential pairs 7, USB7 may be configured as a USB client or as a host, or both, at the
Module designer's discretion.
I/O USB 3.3V Suspend/3.3V USB differential pairs 4
I/O USB 3.3V Suspend/3.3V USB differential pairs 5
O PCIE AC coupled on Module Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE AC coupled off Modul Additional receive signal differential pairs for the SuperSpeed USB data path.
O PCIE AC coupled on Module Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE AC coupled off Modul Additional receive signal differential pairs for the SuperSpeed USB data path.
O PCIE AC coupled on Module Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE AC coupled off Modul Additional receive signal differential pairs for the SuperSpeed USB data path.
O PCIE AC coupled on Module Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE AC coupled off Modul Additional receive signal differential pairs for the SuperSpeed USB data path.
O LVDS LVDS
O LVDS LVDS
LVDS Signals Descriptions
O LVDS LVDS LVDS Channel A differential pairs
O LVDS LVDS
O LVDS LVDS
LVDS Channel A differential clock
O LVDS LVDS LVDS Channel B differential pairs
O LVDS LVDS
O LVDS LVDS
I/O CMOS 3.3V / 3.3V LPC multiplexed address, command and data bus
O LVDS LVDS
O LVDS LVDS
I CMOS 3.3V / 3.3V General purpose input pins.
Power and GND Signal Descriptions
Pin Types
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
VGA Signals Descriptions
Serial Interface Signals Descriptions
Miscellaneous Signal Descriptions
Power and System Management Signals Descriptions
GPIO Signals Descriptions
O CMOS 3.3V / 3.3V General purpose output pins.
I CMOS 3.3V / 3.3V LPC serial DMA request
SPI Signals Descriptions
I CMOS NA Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options of BIOS disable
signals.
LVDS Channel B differential clock
LPC Signals Descriptions