www.dfi.com
15
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
.
w
ol
e
vi
tc
a
,
C
E
D
O
C
o
t
t
u
p
t
u
o
t
e
s
e
R
#
T
E
S
E
R
1
1
ni
p
C
E
D
O
C
o
t
tc
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
0
3
A
#
T
S
R
_
A
D
H
/
C
A
.)
s(
C
E
D
O
C
e
h
t
o
t
la
n
gi
s
n
oi
t
a
zi
n
o
r
h
c
n
y
s-
el
p
m
a
S
C
N
Y
S
0
1
ni
p
C
E
D
O
C
o
t
tc
e
n
n
o
C
V
3
.
3
/
V
3
.
3
S
O
M
C
O
9
2
A
C
N
Y
S
_
A
D
H
/
C
A
.)
s(
C
E
D
O
C
l
a
n
r
e
tx
e
e
h
t
y
b
d
e
t
a
r
e
n
e
g
k
c
ol
c
a
t
a
d
l
ai
r
e
S
K
L
C
_
T
I
B
6
ni
p
C
E
D
O
C
o
t
tc
e
n
n
o
C
V
3
.
3
/
V
3
.
3
S
O
M
C
O
/I
2
3
A
K
L
C
T
I
B
_
A
D
H
/
C
A
.
C
E
D
O
C
e
h
t
o
t
t
u
p
t
u
o
a
t
a
d
M
D
T
l
ai
r
e
S
T
U
O
_
A
T
A
D
S
5
ni
p
C
E
D
O
C
o
t
tc
e
n
n
o
C
V
3
.
3
/
V
3
.
3
S
O
M
C
O
3
3
A
T
U
O
D
S
_
A
D
H
/
C
A
3
3
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
/I
8
2
B
2
N
I
D
S
_
A
D
H
/
C
A
Ω
in series to CODEC2 pin 8 SDATA_IN
3
3
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
/I
9
2
B
1
N
I
D
S
_
A
D
H
/
C
A
Ω
in series to CODEC1 pin 8 SDATA_IN
3
3
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
/I
0
3
B
0
N
I
D
S
_
A
D
H
/
C
A
Ω
in series to CODEC0 pin 8 SDATA_IN
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
3
1
A
+
0
I
D
M
_
0
E
B
G
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
2
1
A
-
0
I
D
M
_
0
E
B
G
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
0
1
A
+
1
I
D
M
_
0
E
B
G
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
9
A
-
1
I
D
M
_
0
E
B
G
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
7
A
+
2
I
D
M
_
0
E
B
G
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
6
A
-
2
I
D
M
_
0
E
B
G
d
n
e
p
s
u
S
x
a
m
V
3
.
3
g
ol
a
n
A
O
/I
3
A
+
3
I
D
M
_
0
E
B
G
GBE0_MDI3-
A
I
2
/O Analog
3.3V max Suspend
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
2
B
#
T
C
A
_
0
E
B
G
Connect to LED and
recommend
current limit
resistor 150
Ω
to 3.3VSB
Gigabit Ethernet Controller 0 activity indicator, active low.
.
w
ol
e
vi
tc
a
,
r
o
t
a
ci
d
ni
k
ni
l
0
r
el
lo
rt
n
o
C
t
e
n
r
e
h
t
E
t
ib
a
gi
G
C
N
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
8
A
#
K
N
I
L
_
0
E
B
G
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
4
A
#
0
0
1
K
N
I
L
_
0
E
B
G
Connect to LED and
recommend
current limit
resistor 150
Ω
to 3.3VSB
Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
5
A
#
0
0
0
1
K
N
I
L
_
0
E
B
G
Connect to LED and
recommend
current limit
resistor 150
Ω
to 3.3VSB
Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
O
6
1
A
+
X
T
_
0
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
O
7
1
A
-
X
T
_
0
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
I
9
1
A
+
X
R
_
0
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
I
0
2
A
-
X
R
_
0
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
O
6
1
B
+
X
T
_
1
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
O
7
1
B
-
X
T
_
1
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
I
9
1
B
+
X
R
_
1
A
T
A
S
r
o
ti
c
a
p
a
c
g
ni
lp
u
o
C
C
A
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
A
T
A
S
I
0
2
B
-
X
R
_
1
A
T
A
S
d
n
e
p
s
u
S
V
3
.
3
o
t
K
7
.
4
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
O
/I
8
2
A
#
T
C
A
_
A
T
A
Connect to LED and
recommend
current limit
resistor 220
Ω
to 3.3V
ATA (parallel and serial) or SAS activity indicator, active low.
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
8
6
A
+
0
X
T
_
E
I
C
P
AC Coupling capacitor
9
6
A
-
0
X
T
_
E
I
C
P
AC Coupling capacitor
8
6
B
+
0
X
R
_
E
I
C
P
9
6
B
-
0
X
R
_
E
I
C
P
4
6
A
+
1
X
T
_
E
I
C
P
AC Coupling capacitor
5
6
A
-
1
X
T
_
E
I
C
P
AC Coupling capacitor
4
6
B
+
1
X
R
_
E
I
C
P
5
6
B
-
1
X
R
_
E
I
C
P
1
6
A
+
2
X
T
_
E
I
C
P
AC Coupling capacitor
2
6
A
-
2
X
T
_
E
I
C
P
AC Coupling capacitor
1
6
B
+
2
X
R
_
E
I
C
P
2
6
B
-
2
X
R
_
E
I
C
P
8
5
A
+
3
X
T
_
E
I
C
P
AC Coupling capacitor
9
5
A
-
3
X
T
_
E
I
C
P
AC Coupling capacitor
8
5
B
+
3
X
R
_
E
I
C
P
9
5
B
-
3
X
R
_
E
I
C
P
8
8
A
+
F
E
R
_
K
L
C
_
E
I
C
P
9
8
A
-
F
E
R
_
K
L
C
_
E
I
C
P
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
9
4
A
#
E
P
P
C
_
0
D
C
X
E
8
4
B
#
E
P
P
C
_
1
D
C
X
E
8
4
A
#
T
S
R
E
P
_
0
D
C
X
E
7
4
B
#
T
S
R
E
P
_
1
D
C
X
E
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
DDI/DP
B71
Connect AC Coupling Capacitors 0.1uF to Device
DDI0_PAIR0-/DP0_LANE0-
B72
Connect AC Coupling Capacitors 0.1uF to Device
DDI/DP
B73
Connect AC Coupling Capacitors 0.1uF to Device
DDI0_PAIR1-/DP0_LANE1-
B74
Connect AC Coupling Capacitors 0.1uF to Device
DDI/DP
B75
Connect AC Coupling Capacitors 0.1uF to Device
DDI0_PAIR2-/DP0_LANE2-
B76
Connect AC Coupling Capacitors 0.1uF to Device
DDI/DP
B81
Connect AC Coupling Capacitors 0.1uF to Device
DDI0_PAIR3-/DP0_LANE3-
B82
Connect AC Coupling Capacitors 0.1uF to Device
7
7
B
+
4
R
I
A
P
_
0
I
D
D
A
N
A
N
8
7
B
-
4
R
I
A
P
_
0
I
D
D
A
N
A
N
1
9
B
+
5
R
I
A
P
_
0
I
D
D
A
N
A
N
2
9
B
-
5
R
I
A
P
_
0
I
D
D
A
N
A
N
3
9
B
+
6
R
I
A
P
_
0
I
D
D
A
N
A
N
4
9
B
-
6
R
I
A
P
_
0
I
D
D
A
N
A
N
I/O PCIE
AC coupled on Module
PD 100K to GND
(S/W IC between Rpu/PCH)
tc
e
n
n
o
c
o
n
s
i
L
E
S
_
X
U
A
_
C
D
D
_
0
I
D
D
f
i
n
oi
tc
n
u
f
+
X
U
A
P
D
+
X
U
A
P
D
o
t
tc
e
n
n
o
C
I/O OD CMOS 3.3V / 3.3V
PU 10K to 3.3V, PD 100K to GND
(S/W IC between Rpu/Rpd
Connect to HDMI/DVI I2C CTRLCLK
HDMI/DVI I2C CTRLCLK if DDI0_DDC_AUX_SEL is pulled high
tc
e
n
n
o
c
o
n
s
i
L
E
S
_
X
U
A
_
C
D
D
_
0
I
D
D
f
i
n
oi
tc
n
u
f
-
X
U
A
P
D
-
X
U
A
P
D
o
t
tc
e
n
n
o
C
V
3
.
3
o
t
K
0
0
1
U
P
el
u
d
o
M
n
o
d
el
p
u
o
c
C
A
E
I
C
P
O
/I
I/O OD CMOS 3.3V / 3.3V
PU 2.2K to 3.3V/PU 100K to 3.3V Connect to HDMI/DVI I2C CTRLDATA
HDMI/DVI I2C CTRLDATA if DDI0_DDC_AUX_SEL is pulled high
tc
e
t
e
D
g
ul
P
-t
o
H
I
D
D
tc
e
t
e
D
g
ul
P
t
o
H
e
ci
v
e
d
o
t
tc
e
n
n
o
C
d
n
a
M
1
D
P
D
N
G
o
t
K
0
0
1
D
P
V
3
.
3
/
V
3
.
3
S
O
M
C
I
9
8
B
D
P
H
_
0
P
D
/
D
P
H
_
0
I
D
D
)I
V
D
/I
M
D
H
(
C
D
D
r
o
f
V
3
.
3
o
t
K
0
0
1
U
P
D
N
G
o
t
M
1
D
P
V
3
.
3
/
V
3
.
3
S
O
M
C
I
5
9
B
L
E
S
_
X
U
A
_
C
D
D
_
0
I
D
D
Selects the function of DDI0_CTRL and DDI0_CTRLDATA_AUX-.
This pin shall have a 1M pull-down to
logic ground on the Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high the AUX pair
contains the CRTLCLK and CTRLDATA signals
************************************************************
DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm
resistor to configure the DDI[n]_AUX pair as the DDC channel.
Carrier DDI[n]_DDC_AUX_SEL should be connected to pin 13 of the DisplayPort
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
6
4
A
+
0
B
S
U
5
4
A
-
0
B
S
U
6
4
B
+
1
B
S
U
5
4
B
-
1
B
S
U
3
4
A
+
2
B
S
U
2
4
A
-
2
B
S
U
3
4
B
+
3
B
S
U
2
4
B
-
3
B
S
U
0
4
A
+
4
B
S
U
9
3
A
-
4
B
S
U
0
4
B
+
5
B
S
U
9
3
B
-
5
B
S
U
7
3
A
+
6
B
S
U
6
3
A
-
6
B
S
U
7
3
B
+
7
B
S
U
6
3
B
-
7
B
S
U
h
ct
i
w
S
r
e
w
o
P
B
S
U
f
o
t
n
e
rr
u
cr
e
v
O
o
t
tc
e
n
n
o
C
B
S
V
3
.
3
o
t
k
0
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
4
4
B
#
C
O
_
1
_
0
_
B
S
U
USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
h
ct
i
w
S
r
e
w
o
P
B
S
U
f
o
t
n
e
rr
u
cr
e
v
O
o
t
tc
e
n
n
o
C
B
S
V
3
.
3
o
t
k
0
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
4
4
A
#
C
O
_
3
_
2
_
B
S
U
USB over-current sense, USB channels 2 and 3. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
h
ct
i
w
S
r
e
w
o
P
B
S
U
f
o
t
n
e
rr
u
cr
e
v
O
o
t
tc
e
n
n
o
C
B
S
V
3
.
3
o
t
k
0
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
8
3
B
#
C
O
_
5
_
4
_
B
S
U
USB over-current sense, USB channels 4 and 5. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
h
ct
i
w
S
r
e
w
o
P
B
S
U
f
o
t
n
e
rr
u
cr
e
v
O
o
t
tc
e
n
n
o
C
B
S
V
3
.
3
o
t
k
0
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
8
3
A
#
C
O
_
7
_
6
_
B
S
U
USB over-current sense, USB channels 6 and 7. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
3
2
B
+
0
X
T
S
S
_
B
S
U
AC Coupling capacitor
2
2
B
-
0
X
T
S
S
_
B
S
U
AC Coupling capacitor
3
2
A
+
0
X
R
S
S
_
B
S
U
2
2
A
-
0
X
R
S
S
_
B
S
U
6
2
B
+
1
X
T
S
S
_
B
S
U
AC Coupling capacitor
5
2
B
-
1
X
T
S
S
_
B
S
U
AC Coupling capacitor
6
2
A
+
1
X
R
S
S
_
B
S
U
5
2
A
-
1
X
R
S
S
_
B
S
U
A
N
A
N
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
6
9
B
T
N
S
R
P
_
T
S
O
H
_
B
S
U
Module USB client may detect the presence of a USB host. A high value (NA for AL9A2)
indicates that a host is present.
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
1
7
A
+
0
A
_
S
D
V
L
2
7
A
-
0
A
_
S
D
V
L
3
7
A
+
1
A
_
S
D
V
L
4
7
A
-
1
A
_
S
D
V
L
5
7
A
+
2
A
_
S
D
V
L
6
7
A
-
2
A
_
S
D
V
L
8
7
A
+
3
A
_
S
D
V
L
9
7
A
-
3
A
_
S
D
V
L
1
8
A
+
K
C
_
A
_
S
D
V
L
2
8
A
-
K
C
_
A
_
S
D
V
L
V
3
.
3
/
V
3
.
3
S
O
M
C
O
7
7
A
N
E
_
D
D
V
_
S
D
V
L
Connect to enable control of LVDS panel power
circuit
LVDS panel power enable
V
3
.
3
/
V
3
.
3
S
O
M
C
O
9
7
B
N
E
_
T
L
K
B
_
S
D
V
L
Connect to enable control of LVDS panel backlight
power circuit.
LVDS panel backlight enable
V
3
.
3
/
V
3
.
3
S
O
M
C
O
3
8
B
L
R
T
C
_
T
L
K
B
_
S
D
V
L
Connect to brightness control of LVDS panel
backlight power circuit.
LVDS panel backlight brightness control
e
s
u
y
al
p
si
d
S
D
V
L
r
o
f
t
u
p
t
u
o
k
c
ol
c
C
2
I
le
n
a
p
S
D
V
L
f
o
k
c
ol
c
C
D
D
o
t
tc
e
n
n
o
C
V
3
.
3
o
t
K
7
.
4
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
D
O
O
/I
3
8
A
K
C
_
C
2
I
_
S
D
V
L
e
s
u
y
al
p
si
d
S
D
V
L
r
o
f
e
ni
l
a
t
a
d
C
2
I
le
n
a
p
S
D
V
L
f
o
a
t
a
d
C
D
D
o
t
tc
e
n
n
o
C
V
3
.
3
o
t
K
7
.
4
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
D
O
O
/I
4
8
A
T
A
D
_
C
2
I
_
S
D
V
L
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
4
B
0
D
A
_
C
P
L
5
B
1
D
A
_
C
P
L
6
B
2
D
A
_
C
P
L
7
B
3
D
A
_
C
P
L
V
3
.
3
/
V
3
.
3
S
O
M
C
O
3
B
#
E
M
A
R
F
_
C
P
L
LPC frame indicates the start of an LPC cycle
8
B
#
0
Q
R
D
_
C
P
L
9
B
#
1
Q
R
D
_
C
P
L
V
3
.
3
/
V
3
.
3
S
O
M
C
O
/I
0
5
A
Q
R
I
R
E
S
_
C
P
L
LPC serial interrupt
V
3
.
3
/
V
3
.
3
S
O
M
C
O
0
1
B
K
L
C
_
C
P
L
LPC clock output - 33MHz nominal
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
3
3
r
o
ts
is
e
r
s
ei
r
e
s
a
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
7
9
B
#
S
C
_
I
P
S
Ω
Connect a series resistor 33
Ω
to Carrier
Board SPI Device CS# pin
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1
3
3
r
o
ts
is
e
r
s
ei
r
e
s
a
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
2
9
A
O
S
I
M
_
I
P
S
Ω
Connect a series resistor 33
Ω
to Carrier
Board SPI Device SO pin
Data in to Module from Carrier SPI
3
3
r
o
ts
is
e
r
s
ei
r
e
s
a
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
5
9
A
I
S
O
M
_
I
P
S
Ω
Connect a series resistor 33
Ω
to Carrier
Board SPI Device SI pin
Data out from Module to Carrier SPI
3
3
r
o
ts
is
e
r
s
ei
r
e
s
a
t
c
e
n
n
o
C
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
4
9
A
K
L
C
_
I
P
S
Ω
Connect a series resistor 33
Ω
to Carrier
Board SPI Device SCK pin
Clock from Module to Carrier SPI
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
O
1
9
A
R
E
W
O
P
_
I
P
S
Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier
4
3
A
#
0
S
I
D
_
S
O
I
B
8
8
B
#
1
S
I
D
_
S
O
I
B
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
S
O
M
C
O
8
9
A
X
T
_
0
R
E
S
5V / 12V(design 3.3v~5V
tolerant)
PD 4.7K
General purpose serial port 0 transmitter
S
O
M
C
I
9
9
A
X
R
_
0
R
E
S
5V / 12V(design 3.3v~5V
tolerant)
General purpose serial port 0 receiver
S
O
M
C
O
1
0
1
A
X
T
_
1
R
E
S
5V / 12V(design 3.3v~5V
tolerant)
PD 4.7K
General purpose serial port 1 transmitter
S
O
M
C
I
2
0
1
A
X
R
_
1
R
E
S
5V / 12V(design 3.3v~5V
tolerant)
General purpose serial port 1 receiver
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
t
u
p
t
u
o
k
c
ol
c
tr
o
p
C
2
I
e
s
o
p
r
u
p
l
a
r
e
n
e
G
B
S
3
V
3
o
t
K
2
.
2
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
O
/I
3
3
B
K
C
_
C
2
I
e
ni
l
O
/I
a
t
a
d
t
r
o
p
C
2
I
e
s
o
p
r
u
p
l
a
r
e
n
e
G
B
S
3
V
3
o
t
K
2
.
2
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
O
/I
4
3
B
T
A
D
_
C
2
I
B
S
3
V
3
o
t
K
0
1
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
O
2
3
B
R
K
P
S
Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.
V
3
.
3
/
V
3
.
3
S
O
M
C
O
7
2
B
T
D
W
Output indicating that a watchdog time-out event has occurred.
V
2
1
/
V
3
.
3
S
O
M
C
D
O
O
1
0
1
B
T
U
O
M
W
P
_
N
A
F
Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.
V
2
1
/
V
3
.
3
S
O
M
C
D
O
I
2
0
1
B
N
I
H
C
A
T
_
N
A
F
Fan tachometer input for a fan with a two pulse output.
C
N
V
3
.
3
/
V
3
.
3
S
O
M
C
I
6
9
A
P
P
_
M
P
T
Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. This signal is used to indicate
Physical Presence to the TPM.
(NC for AL9A2)
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
B
S
3
V
3
o
t
K
0
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
2
1
B
#
N
T
B
R
W
P
A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.
B
S
3
V
3
o
t
K
7
.
4
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
9
4
B
#
T
E
S
E
R
_
S
Y
S
Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
0
5
B
#
T
E
S
E
R
_
B
C
Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.
B
S
V
3
.
3
o
t
K
0
1
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
I
4
2
B
K
O
_
R
W
P
Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
8
1
B
#
T
A
T
S
_
S
U
S
Indicates imminent suspend operation; used to notify LPC devices.
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
5
1
A
#
3
S
_
S
U
S
Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
8
1
A
#
4
S
_
S
U
S
Indicates system is in Suspend to Disk state. Active low output.
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
O
4
2
A
#
5
S
_
S
U
S
Indicates system is in Soft Off state.
.l
a
n
gi
s
p
u
e
k
a
w
s
s
e
r
p
x
E
I
C
P
B
S
V
3
.
3
o
t
K
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
6
6
B
#
0
E
K
A
W
B
S
V
3
.
3
o
t
K
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
7
6
B
#
1
E
K
A
W
General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.
B
S
V
3
.
3
o
t
K
7
.
4
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
7
2
A
#
W
O
L
T
A
B
Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.
ti
w
s
D
I
L
a
r
o
f
m
e
ts
y
s
g
ni
t
a
r
e
p
o
I
P
C
A
e
h
t
y
b
d
e
s
u
l
a
n
gi
s
e
vi
tc
a
w
o
L
.
h
ct
i
w
s
D
I
L
B
S
V
3
.
3
o
t
K
7
4
U
P
V
2
1
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
I
3
0
1
A
#
D
I
L
ch.
B
S
V
3
.
3
o
t
K
0
1
U
P
V
2
1
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
I
3
0
1
B
#
P
E
E
L
S
Sleep button. Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.
.
n
oi
t
a
u
ti
s
p
m
e
t-
r
e
v
o
n
a
g
ni
t
a
ci
d
ni
r
o
s
n
e
s
p
m
e
t
el
u
d
o
M
-f
f
o
m
o
rf
t
u
p
n
I
B
S
V
3
.
3
o
t
K
0
1
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
I
5
3
B
#
M
R
H
T
.
n
w
o
d
t
u
h
s
la
m
r
e
h
t
d
e
r
e
t
n
e
s
a
h
U
P
C
e
h
t
t
a
h
t
g
ni
t
a
ci
d
ni
t
u
p
t
u
o
w
ol
e
vi
tc
A
B
S
V
3
.
3
o
t
K
0
1
U
P
V
3
.
3
/
V
3
.
3
S
O
M
C
O
5
3
A
#
P
I
R
T
M
R
H
T
.e
ni
l
k
c
ol
c
la
n
oi
tc
e
ri
di
b
s
u
B
t
n
e
m
e
g
a
n
a
M
m
e
ts
y
S
B
S
V
3
.
3
o
t
K
2
.
2
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
O
/I
3
1
B
K
C
_
B
M
S
.e
ni
l
a
t
a
d
l
a
n
oi
tc
e
ri
di
b
s
u
B
t
n
e
m
e
g
a
n
a
M
m
e
ts
y
S
B
S
V
3
.
3
o
t
K
2
.
2
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
D
O
O
/I
4
1
B
T
A
D
_
B
M
S
B
S
V
3
.
3
o
t
K
0
1
U
P
V
3
.
3
/
d
n
e
p
s
u
S
V
3
.
3
S
O
M
C
I
5
1
B
#
T
R
E
L
A
_
B
M
S
System Management Bus Alert – active low input can be used to
generate an SMI# (System Management Interrupt) or to wake the system.
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
3
9
A
0
O
P
G
4
5
B
1
O
P
G
7
5
B
2
O
P
G
3
6
B
3
O
P
G
4
5
A
0
I
P
G
PU 47K to 3.3V
3
6
A
1
I
P
G
PU 47K to 3.3V
7
6
A
2
I
P
G
PU 47K to 3.3V
5
8
A
3
I
P
G
PU 47K to 3.3V
n
oi
t
pi
rc
s
e
D
d
r
a
o
B
r
ei
rr
a
C
8
A
9
L
A
e
c
n
a
r
el
o
T
/
li
a
R
r
w
P
e
p
y
T
ni
P
#
ni
P
la
n
gi
S
VCC_12V
A104~A109
B104~B109
Power
4.75V – 20.0V
4.75V – 20.0V
Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.
The module supplies a wide range of power from 4.75V to 20.0V.
V
5
2
.
5
-
V
5
7
.
4
V
5
2
.
5
-
V
5
7
.
4
r
e
w
o
P
7
8
B
~
4
8
B
Y
B
S
_
V
5
_
C
C
V
Standby power input: +5.0V nominal. If VCC5_SBY is used, all
available VCC_5V_SBY pins on the connector(s) shall be used. Only
used for standby and suspend functions. May be left unconnected if
these functions are not used in the system design.
.
V
0
.
3
+
y
ll
a
ni
m
o
N
.
t
u
p
ni
r
e
w
o
p
-t
iu
cr
ic
k
c
ol
c
e
m
it
-l
a
e
R
V
3
.
3
-
V
0
.
2
V
3
.
3
-
V
0
.
2
r
e
w
o
P
7
4
A
C
T
R
_
C
C
V
GND
A1, A11, A21, A31, A41,
A51, A57, A60, A66, A70,
A80, A90, A100, A110, B1,
B11, B21 ,B31, B41, B51,
B60, B70, B80, B90, B100,
B110
Power
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier
Board GND plane.
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect to PCIE device or slot
Device
- Connect AC Coupling cap 0.1uF
Slot
- Connect to PCIE Conn pin
Pin Types
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
Serial Interface Signals Descriptions
Miscellaneous Signal Descriptions
I CMOS
DDI Signals Descriptions
O PCIE
AC coupled off Module
DDI 0 Pair 0 differential pairs/Serial Digital Video B red output differential pair
V
3
.
3
o
t
K
0
1
U
P
A
N
Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options of BIOS disable signals.
LPC Signals Descriptions
O PCIE
AC coupled off Module
DDI 0 Pair 2 differential pairs/Serial Digital Video B blue output differential pair
O PCIE
AC coupled off Module
Connect to Magnetics Module MDI0+/-
Connect to Magnetics Module MDI1+/-
Connect to Magnetics Module MDI2+/-
Connect to Magnetics Module MDI3+/-
Connect to SATA0 Conn RX pin
Connect to SATA1 Conn TX pin
Power and GND Signal Descriptions
I/O CMOS
3.3V / 3.3V
3.3V / 3.3V
LPC serial DMA request
SPI Signals Descriptions
I CMOS
I CMOS
PU 100K to 3V3
General purpose input pins.
Power and System Management Signals Descriptions
GPIO Signals Descriptions
O CMOS
3.3V / 3.3V
General purpose output pins.
LPC multiplexed address, command and data bus
Connect to LPC device
LVDS Channel A differential clock
O LVDS
LVDS
LVDS Signals Descriptions
O LVDS
LVDS
LVDS Channel A differential pairs
O LVDS
LVDS
O LVDS
LVDS
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data path.
I PCIE
AC coupled off Modul
Additional receive signal differential pairs for the SuperSpeed USB data path.
O LVDS
LVDS
I PCIE
I/O USB
3.3V Suspend/3.3V
USB differential pairs 4
I/O USB
3.3V Suspend/3.3V
AC coupled off Modul
Additional receive signal differential pairs for the SuperSpeed USB data path.
O PCIE
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data path.
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
I/O USB
3.3V Suspend/3.3V
USB differential pairs 7
I/O USB
3.3V Suspend/3.3V
USB differential pairs 6
I/O USB
3.3V Suspend/3.3V
USB differential pairs 5
NA for AL9A2
O PCIE
AC coupled off Module
DDI 0 Pair 3 differential pairs/Serial Digital Video B clock output differential pair.
DDI 0 Pair 1 differential pairs/Serial Digital Video B green output differential pair
USB differential pairs 3
I/O USB
3.3V Suspend/3.3V
USB differential pairs 2
I/O USB
3.3V Suspend/3.3V
USB differential pairs 1
USB Signals Descriptions
I/O USB
3.3V Suspend/3.3V
USB differential pairs 0
DDI0_CTRL/
B98
DDI0_CTRLDATA_AUX-/DP0_AUX-
B99
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 2
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 1
O PCIE
PCIE
Reference clock output for all PCI Express and PCI Express Graphics lanes.
NA for AL9A2
NA for AL9A2
ExpressCard Signals Descriptions
I CMOS
3.3V /3.3V
PCI ExpressCard: PCI Express capable card request, active low, one per card
O CMOS
3.3V /3.3V
PCI ExpressCard: reset, active low, one per card
PCI Express Differential Receive Pairs 0
Connect to SATA1 Conn RX pin
Connect to SATA0 Conn TX pin
Connect to PCIE device or slot
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 3
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 3
I PCIE
AC coupled off Module
PCI Express Differential Receive Pairs 2
Device
- Connect AC Coupling cap 0.1uF
Slot
- Connect to PCIE Conn pin
Device
- Connect AC Coupling cap 0.1uF
Slot
- Connect to PCIE Conn pin
Connect to PCIE device or slot
Device
- Connect AC Coupling cap 0.1uF
Slot
- Connect to PCIE Conn pin
Connect to PCIE device or slot
Connect to PCIE device,
PCIe CLK Buffer
or slot
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
Connect 90
�
@100MHz Common Choke in series
and ESD suppressors to GND to USB connector
AC97/HDA Signals Descriptions
Serial TDM data inputs from up to 3 CODECs.
Gigabit Ethernet Signals Descriptions
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec
modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
Serial ATA or SAS Channel 1 receive differential pair.
SATA Signals Descriptions
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 1
PCI Express Lanes Signals Descriptions
Serial ATA or SAS Channel 0 transmit differential pair.
Serial ATA or SAS Channel 0 receive differential pair.
O PCIE
AC coupled on Module
PCI Express Differential Transmit Pairs 0
Serial ATA or SAS Channel 1 transmit differential pair.
I PCIE
AC coupled off Module
