Denon DNP-800NE, Service Manual

Page: 11 / 65

SCH03 CPU
GND LINE POWER- LINE POWER+ LINE ANALOG AUDIO DIGITAL AUDIO STBY POWER
TMS
MD
TDI
TDO
TXD
2 3
JP
E
M
LE
D
6
D
4
D
2
D
1
D
0
KEY
1
KEY
2
TCK
UB
RXD
+3
.3
V
_D
+3
V
3_
C
P
U
R
65
3
0-
160
8
A
IO
S
4_
W
AK
E
U
P
P
_D
O
W
N
I2
C
_S
C
L
I2
C
_S
D
A
DC
_P
R
O
T1
A
_P
W
_C
O
N
T
+16
V
_O
LE
D
D
_P
W
_C
O
N
T
R
65
7
0-
160
8
D
IR
_N
P
C
M
E
L_
D
C
EL_
D
/C
D
IR
_I
N
T
D
IR
_R
ESE
T
E
L_
C
S
EL_
C
S
D
IR
_C
LK
O
LE
D
_D
6
D
IR
_D
O
U
T
O
LE
D
_D
5
O
LE
D
_D
4
M
D
O
LE
D
_D
2
O
LE
D
_D
3
O
LE
D
_D
0
O
LE
D
_D
1
E
L_
R
D
KEY
2
KEY
1
O
LE
D
_D
0
R
E
M
O
TE
R
EM
O
TE
E
L_
R
E
SE
T
E
L_
C
S
LE
D
_R
E
D
LE
D
_RE
D
R
E
M
O
TE
TR
S
T#
O
LE
D
_D
2
O
LE
D
_D
1
G
ND
_D
TM
S
O
LE
D
_D
4
O
LE
D
_D
3
D
G
N
D
G
ND
_D
TC
K
TD
I
O
LE
D
_D
6
O
LE
D
_D
5
D
G
N
D
G
ND
_D
TD
O
O
LE
D
_D
7
IO
EXP
_I
2C
_S
D
A
C
60
7
-
C
60
9
-
R
76
3
10
K-
160
8
R
76
5
4K
7-
160
8
R
76
7
4K
7-
160
8
R
76
8
O
PE
N
R
77
0
4K
7-
160
8
R
77
1
O
PE
N
R
74
3
N
M
+3
.3
V
_D
100
N
-K
-160
8
C
60
5
R
65
5
33
-160
8
0-
160
8
R
75
2
+16
V_
O
LE
D
R
61
7
33
-160
8
R
61
9
33
-160
8
R
66
0
33
-160
8
R
62
1
33
-160
8
C
60
1
100
N
-K
-160
8
R
66
2
33
-160
8
R
62
4
33
-160
8
R
62
6
33
-160
8
30
P
-J
-160
8
C
61
2
R
66
5
33
-160
8
R
62
8
33
-160
8
R
66
7
33
-160
8
R
63
1
33
-160
8
R
66
9
33
-160
8
R
63
3
33
-160
8
R
67
1
33
-160
8
R
67
3
33
-160
8
R
75
8
0-
160
8
R
67
5
33
-160
8
R
76
0
0-
160
8
R
67
6
33
-160
8
+18
V_
O
LE
D
C
59
0
100
N
-K
-160
8
R
68
0
33
-160
8
+3
V
3_
C
P
U
TRST#
GND_D
RESET
+3.3V_CPU
CNVSS
DSP_BOOT
GND_D
RESET
+3.3V_D
P_DOWN
10K-1608 R686
33-1608
R682
R650 33-1608
10K-1608 R647
10K-1608 R644
33-1608 R640
R637 10K-1608
100N-K-1608 C595
4K7-1608
R718
R710
33-1608
0-1608 R699
R695 0-1608
R683
33-1608
33-1608 R651
0-1608
R646
R641 33-1608
DGND
R746
IOEXP_I2C_SCL
IOEXP_I2C_SDA
30K
E3(U)
R
108
7
0-
160
8
HP_DET
LED_RED
LEGO_MODE.
FS1.
FS0.
AL32_TEST5.
AL32_TEST3.
DAC_RST
I2C_SDA
RESET
D
7
D
5
D
3
R749 0-1608
R737 0-1608
R1086 33-1608
C594 100N-K-1608
R703 0-1608
R697 33-1608
R692
33-1608
E_CTS_MIEO
E_RTS_MOEI
E_TXD_MOEI
NET_FACT_RST
NET5V_POWER
DAC1_MUTE
UB
A_PW_SHORT
VARI_ON/OFF
C_PLD_CLK.
C_PLD_MDI.
REMOTE_OUT
PCM_DSD_MODE.
FPGA_VER_CONT.
FS0.
FS1.
FPGA_RESET_IN.
FPGA_RES1.
FPGA_RES2.
FPGA_RES3.
AL32_TEST3.
AL32_TEST4.
EMPHASIS.
HP_ON/OFF
HP_GAIN_M
HP_GAIN_H
I2C_SDA
DAC_RST
HP_DET
I2C_SCL
VARI_ON/OFF
DIR_NPCM
DIR_INT
DIR_RESET
DIR_DOUT
DIR_CE
DIR_DIN
I2C_SDA
AIOS4_WAKEUP
E_TXD_MOEI
E_RXD_MIEO
E_RTS_MOEI
NET_FACT_RST
EMLE
+3.3V_CPU
10K-1608 R708
R704 33-1608
R702 33-1608
10K-1608
R700
33-1608 R649
33-1608 R684
10K-1608 R681
10K-1608 R638
10K-1608 R639
33-1608 R642
33-1608 R645
4R7U-K-10V-1608 C596
C592 100N-K-1608
4K7-1608
R723
R713
33-1608
R705 33-1608
0-1608 R701
33-1608 R685
0-1608
R643
0-1608 R648
ADV
R738
OPEN-1608
R739
OPEN-1608
IOEXP_/INT
REGION
OPTION
R
73
4
10
K-
160
8
R851
NM
10
K-
160
8
R
74
1
R
74
2
10
K-
160
8
AL32_TEST4.
R
65
2
33
-160
8
A
IO
S
4_
S
TBY
_S
TA
TU
S
I2C_SCL
R
65
4
33
-160
8
E
L_
R
D
E
L_
R
E
SE
T
EL_
E,
R
D
R
E
M
O
TE
_O
U
T
D
IR
_D
IN
D
IR
_C
E
O
LE
D
_D
7
E
L_
R
W
R
77
5
0-
160
8
E
L_
D
C
E
L_
R
W
O
LE
D
_P
_C
O
N
T
+18
V
_O
LE
D
LE
D
_G
R
EE
N
+3
V
3_
C
P
U
+3.3
V_
D
R
67
7
0-
160
8
IO
EXP
_/I
N
T
IO
EXP
_I
2C
_S
C
L
O
LE
D
_P
_C
O
N
T
R747 0-1608
R748 0-1608
R740
0-1608
R707 0-1608
R712 0-1608
R715 0-1608
R694
33-1608
R690 33-1608
E_RXD_MIEO
C_PLD_MDO.
C_PLD_CS.
C
60
6
-
C
60
8
-
LEGO_MODE.
FPGA_RES4.
DAC1_MUTE
AL32_TEST5.
DIR_CLK
I2C_SCL
AIOS4_STBY_STATUS
E_CTS_MIEO
R
76
2
4K
7-
160
8
R
76
4
10
K-
160
8
R
76
6
4K
7-
160
8
10K-1608 R687
R
76
9
4K
7-
160
8
4K7-1608
R716
R
74
4
O
PE
N
-160
8
R
74
5
O
PE
N
-160
8
R734
R
73
6
N
M
R
74
6
10
K-
160
8
2.47V
10K
R864
NM
100/25
(6
.3
*11
)-
R
FO
C
69
9
0-
160
8
R
75
1
R
75
4
0-
160
8
100
N
-K
-160
8
C
58
9
EL_
R
ESE
T
R
61
5
33
-160
8
R
61
6
33
-160
8
C
60
2
100
N
-K
-160
8
R
75
5
33
-160
8
R
75
3
0-
160
8
R
65
8
33
-160
8
R
65
9
33
-160
8
R
66
1
33
-160
8
R
66
3
33
-160
8
EL_
R
/W
,W
R
R
61
8
33
-160
8
R
62
0
33
-160
8
R
62
3
33
-160
8
R
62
2
33
-160
8
2 3
1 4
X501
10.000MHZ
R
76
1
10
K-
160
8
C
60
3
1N
-K
-160
8
100
N
-K
-160
8
C
60
4
R
66
4
33
-160
8
R
66
6
33
-160
8
R
66
8
33
-160
8
100
N
-K
-160
8
C
59
1
O
LE
D
_P
_C
on
t
R
62
5
33
-160
8
R
62
7
33
-160
8
R
62
9
33
-160
8
R
63
2
33
-160
8
C
61
3
30
P
-J
-160
8
R
75
9
0-
160
8
R
75
7
0-
160
8
R
75
6
0-
160
8
R
67
0
33
-160
8
R
67
2
33
-160
8
R
67
4
33
-160
8
LE
D
_G
R
EE
N
+3.3
V_
C
PU
+18
V_
O
LE
D
R
63
4
33
-160
8
+3
.3
V
_D
R
67
8
33
-160
8
R
67
9
33
-160
8
TO DIR
BLOCK
+16V_OLED
NET3V3_POWER
A_PW_SHORT
+18V_OLED
A_PW_CONT
+3V3_CPU
C_PLD_DAC1_MUTE.
C_PCM_DSD_MODE.
C_DIR_MCK_SEL.
C_TDM_CONV_RESET.
C_CS2K_LRCK_SEL.
C_CS2K_MCK_SEL.
C_PLD_MDO.
C_PLD_MDI.
C_PLD_CS.
TMS
TRST#
EMLE
MD
UB
TDO
TDI
RESET
HP_GAIN_M
HP_GAIN_H
OPEN 10K
E2(N)
100N-K-1608 C600
R735 0-1608
HP_ON/OFF
R733 0-1608
KEY2
KEY1
TP4
R729 33-1608
R727 33-1608
R726 33-1608
EMPHASIS.
R725
33-1608
R721
33-1608
R717 33-1608
FPGA_RESET_IN.
R714 33-1608
IOEXP_I2C_SCL
IOEXP_/INT FPGA_RES4.
FPGA_RES3.
R709 33-1608
IOEXP_I2C_SDA FPGA_RES1.
FPGA_RES2.
C593
100N-K-1608
R696
33-1608
R691
33-1608
R688
33-1608
R635 2K2-1608
C614
1N-K-1608
R776
220
C598 100N-K-1608
+3.3V_D
EMULATOR
FDT
NET5V_POWER
TO
POWER SHEET
DC_PROT1
D_PW_CONT
DGND
C_DSD_PHASE_MODE.
C_PLD_CLK.
C_USBB_MCK_SEL.
TCK
3.30V 1.64V
100N-K-1608 C599
R728 33-1608
R732 0-1608
R730
100K-1608
LED_GREEN
TP3
R719
33-1608
R724
33-1608
FPGA_VER_CONT.
TP1
R706 33-1608
R711 33-1608
R698 33-1608
R693
33-1608
R689
33-1608
NET3V3_POWER
PCM_DSD_MODE.
R636 2K2-1608
R777
100K-1608
D500
LBAS16HT1G
R774 OPEN
1K-1608
R773
R
75
0
10
K-
160
8
TO FRONT B'D
Q502
RT1N141C
L502
CB05YTYH221-2012
TO FPGA
BLOCK
TO AUDIO
BLOCK
TO LEGO
BLOCK
(ON PCB)
1
2
3
4
5
6
7
8
9
10
11
CP502
1.0-16-11PB-2
TO PLD BLOCK
1
20
2
3
4
5
6
7
8
9
10
19
18
17
11
12
13
14
15
16
IC504
PCF8574PWR
/INT
SCL
NC
SDA
VCC
A0
A1
NC
A2
P7
P6
NC
P5
P4
GND
P3
NC
P2
P1 P0
C597
100N-K-1608
10K 10K
R
77
2
N
M
TP2
1
2
3 4
5
IC505
BD4730G
NC
SUB
GND VOUT
VCC
REMOTE OUT
EARPHONE
JACK501
Q501
RT1P141C
DNP-800NE CPU
1
20
2
3
4
5
6
7
8
9
10
19
18
17
11
12
13
14
15
16
IC503
/INT
SCL
NC
SDA
VCC
A0
A1
NC
A2
P0
P7
P6
NC
P5
P4
GND
P3
NC
P2
P1
PCF8574PWR
100N-K-1608
C610
10N-K-1608
C616
C615
1N-K-1608
22/16(RA2)
C611
1
SW1
NM
1 19 17 15 7 9 11 13 5 3
18 16 14 6 10 4 12 8 2 20
21
24 26 22
23 25 27
CP500
04-6232-127-008-800+
C617
100N-K-1608
1
2
3
4
5
6
7
CP501
04-6227-007-100-801+
143
141
139
137
136
135
134
133
132
130
128
126
124
122
120
118
116
115
114
113
112
111
109
144
142
140
138
131
129
127
125
123
121
119
117
110
1 3 5 7 9 11 13 15 16 18 20 22 24 26 28 30 32 34 36
108 106 104 102 100 98 96 94 93 91 89 87 85 83 81 79 77 75 73
6 4 2 12 10 8 14 21 19 17 29 27 25 23 31 33 35
105 103 107 99 97 95 101 92 90 88 86 84 82 80 78 76 74
38
40
42
44
46
47
48
49
51
53
55
57
59
61
63
65
67
68
69
70
72
37
39
41
43
45
50
52
54
56
58
62
60
64
66
71
R5F5631FDDFB
U503
V
R
E
FL
E
M
LE
VS
S
V
C
L
VBA
TT
X
C
IN
VS
S
V
C
C
VCC_USB
VSS_USB
VSS
VCC
VSS
VCC
VREFL0
VREFH0
AVCC0
3.
V
R
E
FH
R
X
D
_MI232
O
TX
D
_MO
232
I
M
D
X
C
O
U
T
R
ESE
T
X
TA
L
EX
TA
L
RC
_I
N
34
.E
_R
TS
_M
O
E
I
35
.E
_C
TS
_M
IE
O
36
.E
_R
X
D
_M
IE
O
E_TXD_MOEI
NET_FACT_RST
NET5V_POWER
VSS
74.
V
C
C
VS
S
V
C
C
V
C
C
UB
VCC
1.
AVS
S
DC
_P
R
O
T1
A
_P
W
_C
O
N
T
D
_P
W
_C
O
N
T
O
PE
N
TR
S
T#
K
ILL_I
R
TM
S
TD
I
TC
K
TD
O
2.
P
_D
O
W
N
R
E
-ASS
IG
N
AB
LE
R
ESE
R
VE
D
33.
R
ESE
R
VE
D
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
S_FLASH_CLK
RE-ASSIGNABLE
RE-ASSIGNABLE
S_FLASH_HOLD
S_FLASH_WP
S_FLASH_SO
S_FLASH_SI
S_FLASH_CS
MCK_SEL_45/49
DAC1_MUTE
A_PW_SHORT
VARI_ON/OFF
DIR2_GPO
DIR2_DEMP
DIR2_ERR
C_PLD_CLK
C_PLD_MDO
C_PLD_MDI
C_PLD_CS
72.IO
EXP
_I2
C
_S
D
A
73.IO
EXP
_I2
C
_S
C
L
75.IO
EXP
_/I
N
T
OL
E
D
_P
_C
O
N
T
OL
E
D
_D
7
OL
E
D
_D
6
OL
E
D
_D
5
OL
E
D
_D
4
OL
E
D
_D
3
OL
E
D
_D
2
OL
E
D
_D
1
E
L_
C
S
E
L_
R
ESE
T
OL
E
D
_D
0
E
L_
D
C
E
L_
R
D
E
L_
W
R
VS
S
D
IR
_D
IN
D
IR
_D
O
U
T
D
IR
_C
E
D
IR
_C
LK
D
IR
_I
N
T
D
IR
_R
ESE
T
D
IR
_N
P
C
M
D
A
C
2_
R
ESE
T
R
ESE
R
VE
D
104.
R
ESE
R
VE
D
106.I2
C
_S
D
A
107.I2
C
_S
C
L
108.
A
IO
S
4_
W
AKE
U
P
AIOS4_STBY_STATUS
DAC1_RESET
LED_RED
LED_GREEN
HP_DET
REGION
KEY3
KEY2
KEY1
HP_ON/OFF
OPEN
RESERVED
RESERVED
DAC_CLK_SEL
FPGA_S_TEST_3
FPGA_S_TEST_4
FPGA_S_TEST_5
FPGA_DSD_PCM
FPGA_INT_EXT
FPGA_MODE1
FPGA_MODE2
FPGA_MODE3
FPGA_MODE4
FPGA_MODE5
FPGA_MODE6
FPGA_FS0
FPGA_FS1
FPGA_MCK_FS_CONT
FPGA_FS384_CONT
FPGA_DAC_FS_CONT
FPGA_EMPHASIS
RC
O
U
T
R
ESE
R
VE
D
NET3V3_POWER
105.
VS
S
0A
TO A0
1A
TO A1
0B
TO B0
B3
TO 3B
B4
TO 4B
B5
TO 5B
B6
TO 6B
B7
TO 7B
B8 TO 8B
B9
TO 9B
C0
TO 0C
C1
TO 1C
C2
TO 2C
C3
TO 3C
C4
TO 4C
C5
TO 5C
C6
TO 6C
CP500
TO CP100
Before Servicing
This Unit
Electrical
Mechanical
Repair Information
Updating
11