SCH02 FPGA
GND LINE
POWER- LINE
POWER+ LINE
ANALOG AUDIO
DIGITAL AUDIO
STBY POWER
L1
3
E
1
J1
T2
A
6
DGND
DGND
A
7
A
3
B
3
DGND
DGND
TEST1
33_VCCIO
DGND
DGND
DGND
25_VCC
33_VCCIO
12_VCC
DGND
DGND
DGND
DGND
CONT4.
R
59
4
33
-160
8
B8
NCE
FS
1.
FS
1
FP
G
A
_R
ESE
T_
IN
.
FS
0.
FS
0
FTDO
FTDI
FP
G
A
_R
ES
1.
FP
G
A
_R
ES
1
FP
G
A
_R
ES
3.
FP
G
A
_R
ES
3
FTMS
DGND
DGND
FP
G
A
_R
ES
4.
FP
G
A
_R
ES
4
A
L32
_T
ES
T4
.
A
L32_
TES
T4
DGND
A
L32
_T
ES
T5
.
A
L32_
TES
T5
12_VCC
DGND
12_VCC
DGND
12_VCC
DGND
TP
13
DGND
DGND
12_VCC
DGND
MCK_IN
TP
5
TP
14
DGND
12_VCC
DGND
TP
6
DGND
12_VCC
DGND
DGND
33_VCCIO
DGND
DGND
12_VCC
12_VCC
12_VCC
TP
15
NET00279
DGND
25_VCC
DGND
DGND
TP
7
DGND
DGND
DGND
DGND
33_VCCIO
12_VCC
TP
16
TP
8
DGND
DGND
DGND
TP
9
DGND
DGND
D
G
N
D
P
C
M
_D
S
D
_M
O
D
E
.
33
-160
8
R
60
0
P
C
M
_D
S
D
_M
O
D
E
FP
G
A
_VE
R
_C
O
N
T.
FP
G
A
_VE
R
_C
O
N
T
33
-160
8
R
61
3
FP
G
A
_R
ESE
T_
IN
33
-160
8
R
60
5
33
-160
8
R
60
8
33
-160
8
R
61
0
33
-160
8
R
61
1
C
57
1
-
C
56
5
-
-
C
54
3
C
57
4
100
N
-K
-160
8
100
N
-K
-160
8
C
54
6
C
57
7
100
N
-K
-160
8
100
N
-K
-160
8
C
54
9
C
58
0
100
N
-K
-160
8
100
N
-K
-160
8
C
55
2
C
58
3
100
N
-K
-160
8
100
N
-K
-160
8
C
55
5
C
58
6
100
N
-K
-160
8
100
N
-K
-160
8
C
55
8
C
58
8
100
N
-K
-160
8
100
N
-K
-160
8
C
56
0
100
N
-K
-160
8
C
56
1
100
N
-K
-160
8
C
56
3
C
56
8
100
N
-K
-160
8
R720
0-1608
R596
10K-1608
R582
0-1608
H4
FTDI
J5
FTMS
H3
FTCK
F4
NSTATUS
H1
ALTERA_DCLK
D2
H2
DATA0
J3
NCE
H5
NCONFIG
H14
CONF_DONE
FPGA_VER_CONT.
+3.3V_D
33_VCCIO
J1
4
A
13
FPGA_RES1
DGND
33_VCCIO
B
1
A
5
33_VCCIO
12_VCC
DGND
25_VCC
C
3
A
2
DAC_WCK_OUT/DSD_R
DAC_PCM_BCK
DAC_DSD_DATA_L
DAC_PCM_DATA_L
33_VCCIO
PCM_DSD_MODE
+2V5_FPGA
DGND
+3.3V_D
33_VCCIO
33_VCCIO
25_VCC
T6
R7
R6
T7
DSDL
33_VCCIO
C
54
0
100
N
-K
-160
8
R656
NM
R722
NM
R
59
8
1K
-160
8
R
59
7
1K
-160
8
R595
10K-1608
R
59
3
10
K
-160
8
10
K
-160
8
R
59
1
R
59
2
10
K
-160
8
R585
0-1608
R583
0-1608
R581
0-1608
J4
FTDO
L16
C1
CONT4.
ASDO_DATA1
MCK_IN
ALTERA_DCLK
FS1
ASDO_DATA1
FS0
33_VCCIO
LE
GO
_M
O
D
E
.
LE
GO
_M
O
D
E
33_VCCIO
DATA0
33_VCCIO
FTCK
DGND
33_VCCIO
FLASH_NCE_NCSO
AL32_TEST3
EMPHASIS
AL32_TEST5
AL32_TEST4
DGND
FP
G
A
_R
ES
2.
FP
G
A
_R
ES
2
DGND
NCONFIG
DGND
NSTATUS
25_VCC
DGND
33_VCCIO
12_VCC
FPGA_RES2
/INT_EXT
E
M
P
H
AS
IS
.
A
L32
_T
ES
T3
.
A
L32_
TES
T3
E
M
P
H
AS
IS
12_VCC
12_VCC
12_VCC
33_VCCIO
FPGA_RES3
FPGA_RES4
FPGA_VER_CONT
+1V2_FPGA
LEGO_MODE
33_VCCIO
CONF_DONE
33_VCCIO
33_VCCIO
33_VCCIO
T5
R5
12_VCC
R630
0-1608
33
-160
8
R
60
2
33
-160
8
R
60
1
33
-160
8
R
60
7
33
-160
8
R
60
6
33
-160
8
R
60
4
33
-160
8
R
60
3
33
-160
8
R
60
9
33
-160
8
R
61
2
TP
10
TP
11
TP
12
C
57
0
10
U
-K
-10
V
-160
8
C
84
1
100/25
(6.3
*11
)-
R
FO
-
C
54
2
C
54
1
10
U
-K
-10
V
-160
8
C
57
3
100
N
-K
-160
8
C
57
6
100
N
-K
-160
8
C
57
5
100
N
-K
-160
8
C
57
8
100
N
-K
-160
8
100
N
-K
-160
8
C
54
5
100
N
-K
-160
8
C
54
8
100
N
-K
-160
8
C
54
7
100
N
-K
-160
8
C
55
0
C
58
2
100
N
-K
-160
8
C
58
1
100
N
-K
-160
8
C
58
4
100
N
-K
-160
8
100
N
-K
-160
8
C
55
4
100
N
-K
-160
8
C
55
3
100
N
-K
-160
8
C
55
6
C
58
7
100
N
-K
-160
8
100
N
-K
-160
8
C
55
9
100
N
-K
-160
8
C
56
2
C
56
4
10
U
-K
-10
V
-160
8
C
84
0
100/25
(6.3
*11
)-
R
FO
C
56
7
100
N
-K
-160
8
C
56
9
100
N
-K
-160
8
NET00279
25_VCC
TEST1
33_VCCIO
+2V5_FPGA
+3.3V_D
FLASH_NCE_NCSO
D16
PLD_DAC1_PBCK/DBCK.
PCM_BCK/DSD_DBCK_IN
D15
PLD_DAC1_LRCK/DSDL.
PCM_LRCK/DSD_DATA_L_IN
10K-1608
R614
PCM_MCK/DSD_BCK
DAC_PCM_DATA_R
DAC_WCK_OUT/DSD_R
R589
33-1608
DAC_DSD_DATA_L
R586
33-1608
DAC_PCM_DATA_L
DAC_PCM_BCK
WCK/DSD_R
PCM_DATA_L
PCM_BCK
1K
-160
8
R
59
9
PLD_DAC1_MCK.
C16
PLD_DAC1_DATA/DSDR.
PCM_DATA/DSD_DATA_R_IN
FROM
CPU BLOCK
FPGA_RESET_IN
FROM
POWER BLOCK
BD502
CB05YTYH221-2012
BD501
CB05YTYH221-2012
C
83
9
100/25
(6.3
*11
)-
R
FO
R590
33-1608
PCM_MCK/DSD_BCK
R587
33-1608
R584
33-1608
R588
33-1608
DAC_PCM_DATA_R
PCM_DATA/DSD_DATA_R_IN
PCM_BCK/DSD_DBCK_IN
PCM_MCK/DBCK
TO
DAC BLOCK
PCM_DATA_R
From
PLD
1
2
3
4
5
6
7
8
IC502
EPCQ16SA8N
DATA
Vcc
GND
Vcc
Vcc
DCLK
ASDI
nCS
2
4
6
8
7
9
10
1
3
5
04-6244-410-010-846+
FPC501
2
4
6
8
7
9
10
1
3
5
FPC500
1.0-16-10PB-2
C
57
9
100
N
-K
-160
8
C
58
5
100
N
-K
-160
8
C
57
2
-
100
N
-K
-160
8
C
55
1
100
N
-K
-160
8
C
55
7
BD500
CB05YTYH221-2012
100
N
-K
-160
8
C
54
4
DNP-800NE FPGA
C
56
6
100
N
-K
-160
8
0.5MM PITCH
1 MM PITCH
PCM_LRCK/DSD_DATA_L_IN
T1
P1
M1
K1
H1
F1
C1
D1
A1
B1
T2
T3
P3
P2
M3
M2
K2
K3
H2
H3
F2
F3
C2
C3
D2
D3
A2
A3
B2
B3
T4
T5
P5
P4
M4
M5
K4
K5
H4
H5
F4
F5
C4
C5
D4
D5
A4
A5
B4
B5
T6
T7
P6
P7
M6
M7
K6
K7
H6
H7
F6
F7
C6
C7
D6
D7
A6
A7
B6
B7
T8
T9
P8
P9
M8
M9
K8
K9
H8
H9
F8
F9
C8
C9
D8
D9
A8
A9
B8
B9
T10
T11
P10
P11
M10
M11
K10
K11
H10
H11
F10
F11
C10
C11
D10
D11
A10
A11
B10
B11
T12
T13
P12
P13
M12
M13
K12
K13
H12
H13
F12
F13
C12
C13
D12
D13
A12
A13
B12
B13
T14
T15
P14
P15
M14
M15
K14
K15
H14
H15
F14
F15
C14
C15
D14
D15
A14
A15
B14
B15
T16
P16
M16
K16
H16
F16
C16
D16
A16
B16
N1
L1
R1
J1
G1
E1
R2
R3
N3
L3
N2
L2
J2
G2
E2
J3
G3
E3
R4
N4
L4
R5
N5
L5
J4
G4
E4
J5
G5
E5
R6
N6
L6
R7
N7
L7
J6
G6
E6
J7
G7
E7
R8
N8
L8
R9
N9
L9
J8
G8
E8
J9
G9
E9
R10
N10
L10
R11
N11
L11
J10
G10
E10
J11
G11
E11
R12
N12
L12
R13
N13
L13
J12
G12
E12
J13
G13
E13
R14
N14
L14
R15
N15
L15
G14
E14
J15
G15
E15
J14
R16
N16
L16
J16
G16
E16
L
K
J
H
G
F
E
D
C
B
A
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
2
T
R
P
N
M
1
3
4
IC501
EP4CE15F17C8N
6A
A9
B0
B1
B2
Before Servicing
This Unit
Electrical
Mechanical
Repair Information
Updating
10