Denon DN-X600, Service Manual

Page: 72 / 104

72
Pin No BGA Location Pin name I/O Pol Function
78 E14 SHDB8 IO UHPI Data Bus [Lower 16 Bits]
79 E15 AFMCE O N Asynchronous Memory Chip Select
80 E16 EM_RW O N Asynchronous Read/Write
81 F1 CPU_DSP1 I GPIO port DSP-CPU
82 F2 AFSX1 O Not use
83 F3 SHDB19 IO UHPI Data Bus [Upper 16 Bits (IO)]
84 F4 SHDB20 IO UHPI Data Bus [Upper 16 Bits (IO)]
85 F5 DGND DGND
86 F6 DGND DGND
87 F7 DGND DGND
88 F8 DGND DGND
89 F9 DGND DGND
90 F10 DGND DGND
91 F11 DGND DGND
92 F12 DGND DGND
93 F13 SHDB10 IO UHPI Data Bus [Lower 16 Bits]
94 F14 SHDB9 IO UHPI Data Bus [Lower 16 Bits]
95 F15 ASDCE O N SDRAM Chip Select
96 F16 ASDRAS O N SDRAM Row Address Strobe
97 G1 DGND DGND
98 G2 710RST I N ADSP_RST
99 G3 SHDB17 IO UHPI Data Bus [Upper 16 Bits (IO)]
100 G4 SHDB18 IO UHPI Data Bus [Upper 16 Bits (IO)]
101 G5 CVDL CVDL
102 G6 DGND DGND
103 G7 DGND DGND
104 G8 DGND DGND
105 G9 DGND DGND
106 G10 DGND DGND
107 G11 DGND DGND
108 G12 CVDL CVDL
109 G13 SHDB12 IO UHPI Data Bus [Lower 16 Bits]
110 G14 SHDB11 IO UHPI Data Bus [Lower 16 Bits]
111 G15 AEMB0 O SDRAM Bank Address
112 G16 DGND DGND
113 H1 SHDB16 IO UHPI Data Bus [Upper 16 Bits (IO)]
114 H2 DSP16.9M I System clock for DSP 16.9M
115 H3 DGND DGND
116 H4 SHDB31 IO UHPI Data Bus [Upper 16 Bits (IO)]
117 H5 CVDL CVDL
118 H6 DGND DGND
119 H7 DGND DGND
120 H8 DGND DGND
121 H9 DGND DGND
122 H10 DGND DGND
123 H11 DGND DGND
124 H12 CVDL CVDL
125 H13 SHDB14 IO UHPI Data Bus [Lower 16 Bits]
126 H14 SHDB13 IO UHPI Data Bus [Lower 16 Bits]
127 H15 AEMA10 O EMIF Address Bus
128 H16 AEMB1 O SDRAM Bank Address
129 J1 OSCVSS DGND