Denon DN-X1600, Service Manual, Page: 79 / 115

79
Pin No BGA Location Pin name I/O Pol Function
192 M16 FEMA1 I 13bits address bus (DSP)
193 N1 SHDB13.. IO 16bits data bus (CPU)
194 N2 SHDB9.. IO 16bits data bus (CPU)
195 N3 SHDB7.. IO 16bits data bus (CPU)
196 N4 M1 PU Configuration reserve pin (Pull up)
197 N5 BFRAME_1 I SPDIF user bit trigger (DIR9001)
198 N6 FEMD10 IO 24bits data bus (DSP)
199 N7 FEMD11 IO 24bits data bus (DSP)
200 N8 FEMD12 IO 24bits data bus (DSP)
201 N9 FEMD13 IO 24bits data bus (DSP)
202 N10 FEMD15 IO 24bits data bus (DSP)
203 N11 FEMD16 IO 24bits data bus (DSP)
204 N12 FEMD17 IO 24bits data bus (DSP)
205 N13 FEMA7 I 13bits address bus (DSP)
206 N14 FEMA4 I 13bits address bus (DSP)
207 N15 V3FPG VCCO
208 N16 FEMA0 I 13bits address bus (DSP)
209 P1 SHDB14.. IO 16bits data bus (CPU)
210 P2 SHDB10.. IO 16bits data bus (CPU)
211 P3 DGND DGND
212 P4 M0 PU Configuration reserve pin (Pull up)
213 P5 FEMD7 IO 24bits data bus (DSP)
214 P6 FEMD8 IO 24bits data bus (DSP)
215 P7 FEMD9 IO 24bits data bus (DSP)
216 P8 710LRCK I LR clock from DSP
217 P9 FEMD18 IO 24bits data bus (DSP)
218 P10 FEMD19 IO 24bits data bus (DSP)
219 P11 FEMD20 IO 24bits data bus (DSP)
220 P12 FEMD21 IO 24bits data bus (DSP)
221 P13 FEMD22 IO 24bits data bus (DSP)
222 P14 DGND DGND
223 P15 LCD_LED O LCD's LED control
224 P16 FEMD31 NC
225 R1 SHDB15.. IO 16bits data bus (CPU)
226 R2 M2 PU Configuration reserve pin (Pull up)
227 R3 FEMD5 IO 24bits data bus (DSP)
228 R4 V3FPG VCCO
229 R5 FEMD6 IO 24bits data bus (DSP)
230 R6 DGND DGND
231 R7 24.6M I 24.576MHz master clock
232 R8 V3FPG VCCO
233 R9 FEMD23 IO 24bits data bus (DSP)
234 R10 DGND DGND
235 R11 DOUT REV Configuration reserve pin
236 R12 V3FPG VCCO
237 R13 NC NC
238 R14 CCLK REV Configuration reserve pin
239 R15 NC NC
240 R16 SUSPEND REV Conservation of energy control (NC)
241 T1 DGND DGND
242 T2 FEMD0 IO 24bits data bus (DSP)
243 T3 FEMD1 IO 24bits data bus (DSP)
244 T4 FEMD2 IO 24bits data bus (DSP)