Denon DN-F450R, Service Manual, Page: 53 / 67

53
PLL1707DBQ (MAIN : IC402)
PLL1707DBQ Block Diagram
PLL1707DBQ Pin Function
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
V
CC
AGND
XT1
V
DD
3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
V
DD
2
CSEL
XT2
Mode Control Interface
( ): PLL1708
XT1
(MS)
SR
(MC)
FS2
(MD)
FS1 CSEL
PLL2
PLL1 OSC
XT2
MCKO1 MCKO2 SCKO0
Divider Divider Divider
SCKO1
SCKO2
SCKO3
Reset
Power Supply
VCC AGND VDD1–3 DGND1–3
TERMINAL
I/O DESCRIPTION
NAME NO.
I/O DESCRIPTION
AGND 9 – Analog ground
CSEL 12 I SCKO1 frequency selection control(1)
DGND1 4 – Digital ground 1
DGND2 16 – Digital ground 2
DGND3 17 – Digital ground 3
MC 6 I Bit clock input for serial control(1)
MCKO1 14 O 27-MHz master clock output 1
MCKO2 15 O 27-MHz master clock output 2
MD 5 I Data input for serial control(1)
MS 7 I Chip select input for serial control(1)
SCKO0 18 O System clock output 0 (33.8688 MHz fixed)
SCKO1 19 O System clock output 1 (selectable for 48 kHz)
SCKO2 2 O System clock output 2 (256 fS selectable)
SCKO3 3 O System clock output 3 (384 fS selectable)
VCC 8 – Analog power supply, 3.3 V
VDD1 1 – Digital power supply 1, 3.3 V
VDD2 13 – Digital power supply 2, 3.3 V
VDD3 20 – Digital power supply 3, 3.3 V
XT1 10 I 27-MHz crystal oscillator, or external clock input
XT2 11 O 27-MHz crystal oscillator, must be OPEN for external clock input mode
(1) Schmitt-trigger input with internal pulldown.